Termination circuits and methods for memory buses and devices

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Details

326 58, 326 86, 326 90, 327321, H03K 19003, H03K 190175

Patent

active

061007137

ABSTRACT:
An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor. The first threshold reference device being configured to maintain a base of the first clamping transistor at about V.sub.BE lower than the second reference voltage level. There is further included a second threshold reference device coupled to the second clamping transistor, the second threshold reference device being configured to maintain a base of the second clamping transistor at about V.sub.BE higher than the first reference voltage level.

REFERENCES:
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patent: 5179229 (1993-01-01), Tipon
patent: 5206544 (1993-04-01), Chen et al.
patent: 5214320 (1993-05-01), Truong
patent: 5528190 (1996-06-01), Honningford
patent: 5760601 (1998-06-01), Frankeny

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