Termination circuit for word lines of a semiconductor memory dev

Details Termination circuit for word lines of a semiconductor memory dev Termination circuit for word lines of a semiconductor memory dev

1980-08-29

1983-01-25

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365179, 365190, G11C 1140, G11C 700

Patent

active

043707360

ABSTRACT:
A termination circuit for word lines of a static semiconductor memory device comprising, for each word line, a first transistor which detects a potential change on the word line, a delay circuit which delays an output signal from the first transistor by a predetermined time period and a second transistor which is turned on and off by an output signal from the delay circuit. Each of the second transistors is connected between one of the hold lines and a common hold current source, so that the second transistors and the common hold current source forming a current switch.

REFERENCES:
patent: 4156941 (1979-05-01), Homma et al.
patent: 4164791 (1979-08-01), Homma
patent: 4168539 (1979-09-01), Anderson
Inadachi et al., "A 6ns 4kb Bipolar RAM Using Switched Load Resistor Memory Cell", ISSCC Digest of Technical Papers, Feb. 15, 1979, p. 108.
Buerker et al., "An ECL 100K Compatible 1024.times.4b RAM with 15ns Access Time", ISSCC Digest of Technical Papers, Feb. 15, 1979, p. 102.

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