Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2010-01-11
2011-11-22
Crawford, Jason M (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S081000, C326S087000, C326S113000, C327S109000, C327S112000
Reexamination Certificate
active
08063658
ABSTRACT:
In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.
REFERENCES:
patent: 6021071 (2000-02-01), Otsuka
patent: 6037798 (2000-03-01), Hedberg
patent: 6433619 (2002-08-01), Akita et al.
patent: 6605958 (2003-08-01), Bergman et al.
patent: 6642740 (2003-11-01), Kim et al.
patent: 6670828 (2003-12-01), Ramaswamy
patent: 6894529 (2005-05-01), Chong et al.
patent: 6903581 (2005-06-01), Clark et al.
patent: 7034567 (2006-04-01), Jang
patent: 7064576 (2006-06-01), Maangat
patent: 7078943 (2006-07-01), Ho et al.
patent: 7154981 (2006-12-01), Tokuhiro et al.
patent: 7161865 (2007-01-01), Fujisawa
patent: 7282791 (2007-10-01), Funaba et al.
patent: 7282955 (2007-10-01), Kim
patent: 7318183 (2008-01-01), Ito et al.
patent: 7368937 (2008-05-01), Song
patent: 7372294 (2008-05-01), Kim
patent: 7391230 (2008-06-01), Kobayashi
patent: 7403040 (2008-07-01), Park et al.
patent: 7429881 (2008-09-01), Deng et al.
patent: 7459929 (2008-12-01), Chung
patent: 7495468 (2009-02-01), You
patent: 7495469 (2009-02-01), Park
patent: 7612604 (2009-11-01), Miyazaki et al.
patent: 2002/0175700 (2002-11-01), Nagano et al.
patent: 2003/0042573 (2003-03-01), Fan et al.
patent: 2003/0189441 (2003-10-01), Nguyen et al.
patent: 2004/0004494 (2004-01-01), Song
patent: 2004/0141391 (2004-07-01), Lee et al.
patent: 2004/0227205 (2004-11-01), Walmsley
patent: 2005/0099834 (2005-05-01), Funaba et al.
patent: 2005/0225353 (2005-10-01), Kwon
patent: 2005/0226080 (2005-10-01), Lee
patent: 2005/0248362 (2005-11-01), Choe
patent: 2006/0053243 (2006-03-01), David et al.
patent: 2006/0091900 (2006-05-01), Kang et al.
patent: 2006/0132171 (2006-06-01), Nguyen
patent: 2006/0232294 (2006-10-01), Song
patent: 2007/0164844 (2007-07-01), Lin et al.
patent: 2007/0205848 (2007-09-01), Park et al.
patent: 2008/0211535 (2008-09-01), King
patent: 2008/0258756 (2008-10-01), Kobayashi
patent: 2008/0278193 (2008-11-01), Park et al.
patent: 2008/0284465 (2008-11-01), Kao
patent: 2008/0290894 (2008-11-01), Sohn
patent: 2008/0303546 (2008-12-01), Millar
patent: 2008/0315978 (2008-12-01), Knight et al.
patent: 2009/0009212 (2009-01-01), Brox
patent: 2009/0015290 (2009-01-01), Park
patent: 2010/0066404 (2010-03-01), Zhang et al.
patent: 03/017112 (2003-02-01), None
patent: PCT/CA2010/000027 (2010-03-01), None
Ho Young Song et al., “A 1.2Gb/s/pin Double Data Rate SDRAM with On-Die Termination”, ISSCC 2003 / Session 17 / SRAM and DRAM / Paper 17.8, Feb. 12, 2003, © 2003 IEEE, 2003 IEEE International Solid-State Circuits Conference, 10 pages.
Yen-Sung Michael Lee, “Application of Active Inductors in High-Speed I/O Circuits”, Thesis submitted in partial fulfillment of the requirements for the degree of Master of Applied Science in the Faculty of Graduate Studies (Electrical and Computer Engineering), The University of British Columbia (Vancouver), Oct. 2008, © Yen-Sung Michael Lee, 2008, 77 pages.
Ambrish Kant Varma, “Improved Behavioral Modeling Based on the Input Output Buffer Information Specification”, A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the Degree of Doctor of Philosophy, Computer Engineering, Raleigh, NC, 2007, 191 pages.
“OP-Amp Output Limitations”, (Section 7.11 in text), http://www.optics.arizona.edu/opti360/Week%209.pdf, The University of Arizona, College of Optical Sciences, OPTI 360 Electronics for Optical Engineers and Scientists, Fall 2008, 19 pages.
Samsung Electronics, “DDR2 Application Note ODT (On Die Termination) Control”, Mar. 2006, Product Planning & Application Engineering Team, Memory Division, Samsung Electronics Co., Ltd., 12 pages.
Wikipedia, “On-die termination”, http://en.wikipedia.org/wiki/On-die—termination, downloaded on Mar. 9, 2009, 2 pages.
National Instruments, “Proper Termination for High-Speed Digital I/O Applications”, Sep. 6, 2006, http://zone.ni.com/devzone/cda/tut/p/id/3854, downloaded on Mar. 9, 2009, 4 pages.
Elpida, “New Function of DDR2 SDRAM On Die Termination (ODT)”, Document No. E0593E10 (Ver. 1.0), Jan. 2005, Japan, http://www.elpida.com, © Elpida Memory, Inc. 2005, 12 pages.
Rambus, “On Die Termination (ODT) Calibration”, http://www.rambus.com/kr/patents/innovations/detail/odt—calib.html, downloaded on Mar. 9, 2009, Copyright 2009 Rambus Inc., 3 pages.
JEDEC, “DDR2 SDRAM Specification”, JESD79-2B (Revision of JESD79-2A), Jan. 2005, © JEDEC Solid State Technology Association 2005, 113 pages.
JEDEC, “DDR3 SDRAM Specification”, JESD79-3B (Revision of JESD79-3A, Sep. 2007), Apr. 2008, © JEDEC Solid State Technology Association 2007, 200 pages.
Crawford Jason M
Mosaid Technologies Incorporated
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