Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-04-17
2007-04-17
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C362S021000, C365S189011
Reexamination Certificate
active
11162023
ABSTRACT:
A circuit for terminating devices attached to a signal line and driving a load includes a resistor R1in series with the signal line circuit CR1having a resistor in series with a switch wherein CR1is in parallel with R1, a circuit CR2having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CR3having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CR4having a resistor in series with a switch, connected at one end to ground and at the other to the load, a circuit CR5having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, and a capacitor connected between the receiver or transmitter and ground.
REFERENCES:
patent: 5220211 (1993-06-01), Christopher et al.
patent: 5982192 (1999-11-01), Saito
patent: 6157688 (2000-12-01), Tamura et al.
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6853213 (2005-02-01), Funaba
patent: 6937111 (2005-08-01), Kwon
patent: 7058131 (2006-06-01), Dreps et al.
Tan Vibol
White Mark P.
LandOfFree
Termination arrangement for high speed data rate multi-drop... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Termination arrangement for high speed data rate multi-drop..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Termination arrangement for high speed data rate multi-drop... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3764325