Terminal mapping apparatus

Details Terminal mapping apparatus Terminal mapping apparatus

1997-03-26

1999-11-16

Hua, Ly V.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 7, 714 8, 365201, 365 63, G11C 1700, G06F 1120

Patent

active

059876239

ABSTRACT:
A memory module comprises a plurality of memory chips, data input/output terminals, and switching means. One word in a memory chip comprises a plurality of bits, and each memory chip includes a number of input/output terminals corresponding to one word. The number of data input/output terminals is less than the total number of input/output terminals of the memory chips. Switching means switches a connection between input/output terminals of the memory chips and data input/output terminals. Only those input/output terminals of the memory chips which are connected to non-defective bits are connected to the data input/output terminals.

REFERENCES:
patent: 3845476 (1974-10-01), Boehm
patent: 4656605 (1987-04-01), Clayton
patent: 4884237 (1989-11-01), Mueller et al.
patent: 4992984 (1991-02-01), Busch et al.
patent: 5051994 (1991-09-01), Bluethman et al.
patent: 5199033 (1993-03-01), McGeoch et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5278793 (1994-01-01), Yeh
patent: 5504373 (1996-04-01), Oh et al.

Affiliated with

Also associated with

Rating

Terminal mapping apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Terminal mapping apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Terminal mapping apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1338785