Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
1999-10-12
2001-06-19
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S690000, C257S734000
Reexamination Certificate
active
06249045
ABSTRACT:
TECHNICAL FIELD
The present invention is concerned with a circuitized substrate having plated through-holes wherein plated through-holes are tented with a dielectric polymer film. Tenting of plated through-holes makes it possible to use the real estate above the tented plated through-holes for wiring and/or bonding pads. In addition, the present invention is concerned with a method for tenting plated though-holes with a dielectric polymeric film.
BACKGROUND OF INVENTION
Increasing levels of integration of integrated circuit chips reduces the chip count of a functional circuit, while significantly increasing the I/O count of the individual integrated circuits making up the functional circuit. This drive for increased circuit and component density in the individual integrated circuit chips leads to a parallel drive for increased circuit and component density in the printed circuit boards carrying the chips and in the assemblies using them.
Many applications in electronic packaging including laminate chip carriers are being constrained in their ability to escape the desired number of I/O. These constraints include line widths, line spaces, plated through-hole diameters and plated through-hole capture pad diameters. Plated through-holes are typically limited in their size by the ability of small drills, and the inability to plate holes of high aspect ratios (hole length/divided by hole diameter). Line widths/spaces are typically limited by photo lithographic constraints including the tendency for yields to decrease with decreased line widths.
The increase circuit and component density in the printed circuit boards makes the ability to locate either solder surface mount components or place additional circuitry layers directly above plated through-holes highly desirable. This is especially the case when the density of the plated through-holes required to service the I/O's of the surface mount components is such that there is no surface area available for attachment pads interstitial to the plated through-hole grid.
This problem is especially severe with fine pitch ball grid array components (BGA) and flip chip attach (FCA) integrated circuits.
It would therefore be desirable to provide for the tenting of plated through-holes by a dielectric layer.
SUMMARY OF INVENTION
The present invention provides for the tenting of plated through-holes which in turn allows using the real estate above the plated through-hole for wiring and/or bonding pads. This is especially advantageous when it is desired to feed power through plated through-holes directly beneath the chip and have a full grid BGA package. Since the area of
1
BGA pad is large compared to the array of power and ground C
4
s, a dielectric layer is required to isolate BGA pads from the plated through-holes under the chip. Of course, outside the chip footprint, the locations of plated through-holes can be chosen to avoid this concern.
According to the present invention, plated through-holes are tented with a layer of dielectric thermosettable polyimide composition. The use of the thermosettable polyimide makes it possible to employ relatively thin films along with the ability to withstand the relatively high temperatures used for a subsequent C
4
chip attachment.
In addition, the present invention is concerned with a process for tenting plated through-holes with a polymer film which comprises the steps of:
providing a circuitized substrate having plated through-holes;
applying a first layer of a thermoplastic polyimide material onto a surface of the circuitized substrate;
providing a new layer of a sacrificial carrier material;
applying and partially curing a second layer of polyimide material on a surface of the sacrificial carrier material;
bringing the first layer of polyimide material into contact with the second layer of polyimide material and laminating to thereby bond together the first and second layers of polyimide material;
removing the layer of the sacrificial carrier material;
and curing the thermosettable polyimide material.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
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patent: 5443672 (1995-08-01), Stoll et al.
patent: 5561323 (1996-10-01), Andros et al.
patent: 5618636 (1997-04-01), Watanabe et al.
patent: 5633206 (1997-05-01), Kim et al.
patent: 5861663 (1999-01-01), Isaacs et al.
Fink, Peter, Designrules SPT MCM-L Technologie Handbook, STP Abteilung 6590, Version 1.0, Jan. 20, 1996, Jan. 12, 1995.
Kresge John S.
Stone David B.
Wilcox James R.
Collins D. M.
Connolly Bove & Lodge & Hutz LLP
International Business Machines - Corporation
Picardat Kevin M.
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