Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2000-02-04
2001-08-07
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S149000
Reexamination Certificate
active
06272039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates a memory cell and, more particularly, is related to an apparatus and method using advanced capacitor dielectrics in the construction of a random access memory (RAM) memory cell.
2. Description of Related Art
As is well known in the art, there are basically two types of metal oxide semiconductor (MOS) random access memories (RAMS): static and dynamic. A static RAM or SRAM is a form of semiconductor memory based on the logic circuit known as a flip-flop, which retains information as long as there is enough power to operate the device. These flip-flops have to be simple in order to minimize the silicon area per cell, which is very important since the cell array constitutes by far the largest part of the memory chip. One problem with standard SRAMs is their large size, owing to the use of six transistors in each memory cell where all six are aligned in one plane of the silicon wafer containing them.
Dynamic RAMs (DRAMs) on the other hand store binary data on capacitors resulting in a further reduction in cell area at the expense of more elaborate read/write circuitry. The binary data stored in DRAMs is in the form of the charge on the capacitor. Due to various leakage effects (i.e. current drain) that are inevitably present, the capacitor charge will eventually leak off. Thus, to ensure proper operation of DRAMs, a refresh operation must be completed periodically.
During the refresh operation, the DRAM memory cells' content is read and the data stored therein is rewritten, thus restoring the capacitor charge to its proper value. The refresh operation must be performed every few milliseconds (e.g. eight to sixteen milliseconds) and thus implies the necessity of having a clock connection to the DRAM circuit. This periodic refresh operation required in the DRAMs operation requires that additional refresh circuitry be included in the design, thereby increasing the surface area of the circuit.
Regardless of the refresh operation, DRAMs are preferred over SRAMs. This is because the DRAM memory cell has significantly fewer components and as a result, the DRAMs achieve greater packing density than is possible with any static RAM. Despite being slower, DRAMs are more commonly used than SRAMs because of the smaller DRAM cell design that allows a DRAM to hold up to four times as much data as a SRAM within the same surface area on the integrated circuit.
However, there have been problems in the past constructing capacitors on integrated circuits for usage in a RAM. Discrete capacitors using high dielectric constant films of Silicon (Si) and Silicon Oxide (SiO
2
) have been studied since the 1950s. Nevertheless, incompatibilities with the Si—SiO
2
technology progression have inhibited these dielectrics from being used in an integrated circuit manufacturing environment.
Several attempts have been made to merge high dielectric discrete capacitors and DRAM technologies in a brute force manner by either inserting existing access-transistor and stacked-capacitor fabrication modules below the first level metal interconnect of their Application Specific Integrated Circuit (ASIC) technology or by burying a trench-capacitor underneath an access-transistor.
The first approach leads to a technology that has a high mask count, and is somewhat problematic because of the introduction of additional thermal cycles to the fabrication process and the increased aspect ratio of the contact window etch in the first level metal interconnect intended for the ASIC transistors.
The trench-capacitor approach is more reasonable from a processing point of view, however, it is not considered scalable. This scalability problem is due to difficulty associated with depositing advanced dielectrics in a deep trench.
Heretofore, manufactures have been unable to fulfill the aspiration of providing a RAM memory cell with temperature insensitivity and a high speed of access along with reduced circuit complexity and size.
SUMMARY OF THE INVENTION
Certain advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
To achieve the advantages and novel features, the present invention is generally directed to an apparatus and method for the utilization of a capacitor as a load element in a temperature insensitive memory cell. In the context of the present invention, “load element” is used to indicate that semiconductor current (which is not quantum tunneling related) is passed through the capacitor to the transistor.
Briefly described, in architecture, the system can be implemented as follows. A temperature insensitive capacitor load memory cell utilizes a capacitor to obtain an offset current path through an analogous parasitic resistor of sufficient magnitude to offset other leakage currents from one or more transistors of the memory cell. This offset current, along with a particular capacitor/transistor interconnection, will regulate the logic levels in the memory cell to settle the memory cell into a static state. The capacitor has a temperature dependent capacitor leakage that tracks the current leakage of the one or more transistors of the memory cell, as the one or more transistors vary with temperature.
The present invention can also be viewed as providing a method for constructing a temperature insensitive memory cell. In this regard, the following steps can broadly summarize the method. First, a substrate is provided. Next, a source contact and a drain contact are formed on the substrate using a field oxide layer. A gate electrode is formed on top of the field oxide to create a transistor. A first contact is formed on the source contact. Next, a first metal layer bit line is formed on the first contact to connect the first contact to the first metal layer bit line. A second contact is formed on the drain contact. A first plug is fabricated on the second contact, and a capacitor is formed on the first plug. The capacitor includes a dielectric having a temperature dependent capacitor leakage that tracks a current leakage of the transistor as the transistor varies with temperature. Next, a second metal layer is formed on the capacitor. A second plug is fabricated on the second metal layer, and a third metal layer is formed on the second plug.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention
REFERENCES:
patent: 3662356 (1972-05-01), Michon et al.
patent: 4223333 (1980-09-01), Masuoka
patent: 5485420 (1996-01-01), Lage et al.
patent: 5825684 (1998-10-01), Lee
patent: 551756A1 (1993-07-01), None
patent: 0609081A2 (1994-08-01), None
patent: 61-224196 (1986-10-01), None
Clemens James T.
Diodato Philip W.
Wong Yiu-Huen
Agere Systems Guardian Corp.
Le Thong
Phan Trong
Thomas Kayden Horstemeyer & Risley LLP
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