Temperature detecting circuit and dynamic random access memory d

Details Temperature detecting circuit and dynamic random access memory d Temperature detecting circuit and dynamic random access memory d

1993-01-21

1994-12-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365212, 365194, 327512, G11C 700

Patent

active

053750934

ABSTRACT:
Delay circuit 11 is composed of eight-stage NOT circuits. Polysilicon resistors RPS11 and RPS12 are connected to the sources of P channel type MOS transistor Qp12 and N channel type MOS transistor Qn12 in the second stage NOT circuit. These polysilicon resistors exhibit a smaller temperature dependency, as shown by dot lines in FIG. 2. The delay time of the eight-stage NOT circuits as a whole shows a smaller temperature dependency. Delay circuit 12 in FIG. 1 is composed of three-stage NOT circuit, followed by three-stage NOT circuit or one-stage NOT circuit. With such arrangement, a temperature detection circuit with no or less manufacturing deviations is completed. By utilization of this circuit, the refresh interval of self-refresh operation of a DRAM at low temperature may be expanded to be a multiple integer longer than a given reference interval to assure self-refresh operation at the optimum refresh interval within a wide range of temperature, and power consumption of the DRAM may be reduced at low temperature.

REFERENCES:
patent: 4453237 (1984-06-01), Reese et al.
patent: 4547867 (1985-10-01), Reese et al.
patent: 4716551 (1987-12-01), Inagaki
patent: 4883992 (1989-11-01), Koglin et al.

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