Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-12-30
2004-08-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S194000, C365S211000, C327S512000
Reexamination Certificate
active
06778456
ABSTRACT:
BACKGROUND
1. Technical Field
The present disclosure relates to a temperature detecting circuit and, more particularly, to a temperature detecting circuit that is capable of selecting an optimum detector from a plurality of detectors by detecting temperatures and predicting delay variations within a possible range based on process parameters or variations in the voltage.
2. Description of the Related Art
In nonvolatile memory devices, stored data is maintained during a periodic refresh operation. A self-refresh operation requires a relatively large amount of standby current. For a refresh period, however, many differences in current exist based on temperature. If the temperature is detected and the refresh period is then changed in response to the detected temperature, the standby current may be greatly reduced. The accuracy of the temperature detector may be reduced based on external conditions such as process, voltage, and the like.
FIG. 1
is an exemplary circuit diagram that depicts a conventional temperature detecting circuit. A temperature detecting signal (compare) includes a signal that is internally produced to periodically measure the temperature, or it may include an externally inputted signal. The temperature detecting signal (compare) may be generated when the temperature is detected. In operation, the temperature detecting signal (compare) is applied to a first delay circuit
10
, a second delay circuit
30
, and a third delay circuit
40
. The temperature detecting signal that is delayed in the first delay circuit
10
is then provided as an input to a pulse generator
20
. The pulse generator
20
generates first and second pulse signals (lat and latb) in response to the delayed temperature detecting signal. In addition, each of the second delay circuit
30
and the third delay circuit
40
delays the temperature detecting signal to produce delayed signals (F
1
and F
2
), respectively. The second delay circuit
30
is relatively sensitive to variations in temperature and voltage, while the third delay circuit
40
is relatively insensitive to variations in temperature and voltage.
Generally, the second delay circuit
30
includes a plurality of inverters. In the second delay circuit
30
, a signal transfer is delayed when the temperature is high or the voltage is low. The third delay circuit
40
includes a plurality of NMOS transistors, a plurality of PMOS transistors, and a plurality of inverters. As discussed above, the third delay circuit
40
is relatively insensitive to variations in temperature or voltage. Outputs generated by the second delay circuit
30
and the third delay circuit
40
are compared in a detector
50
. The detector
50
determines whether the detected temperature is higher or lower than a reference temperature based on the output. For example, in a state where the second delay circuit
30
and the third delay circuit
40
have generally similar characteristics at a specific temperature, if the detected temperature is higher than the specific temperature, the delayed temperature detecting signal F
1
may reach the detector
50
slower than the delayed temperature detecting signal F
2
. Thus, a node F
3
of the detector
50
has a HIGH state. The potential at the node F
3
is stored at the latch
50
a
based on the first and second pulse signals (lat and latb) generated by the pulse generator
20
. The refresh controller
60
performs the refresh operation based on the output (Temp_det) of the latch
50
a.
Unfortunately, the characteristics of the second delay circuit
30
and the third delay circuit
40
may change depending on the process parameters, variations in voltage, and the like. Thus, the detected temperature may be different depending on the particular device.
SUMMARY
A temperature detector is adapted to select an optimum detector from a plurality of detectors by detecting the temperature using the plurality of detectors and predicting delay variations within a certain range depending on process parameters or variations in the voltage. The temperature detector includes a pulse generator adapted to generate pulse signals in response to temperature detecting signals, a first delay circuit adapted to delay the temperature detecting signals in accordance with different delay times and generate a plurality of delayed signals, a second delay circuit adapted to delay the temperature detecting signals and generate a plurality of delayed signals, a plurality of detectors adapted to compare the plurality of delayed signals generated by the first and second delay circuits and generate compared values based on the pulse signals, a plurality of pads adapted to read the compared values generated by the plurality of detectors, and a comparison unit adapted to compare the temperature values read from the plurality of pads and current temperature values and determine an optimum detector that generates an optimum temperature value.
REFERENCES:
patent: 4868525 (1989-09-01), Dias
patent: 5375093 (1994-12-01), Hirano
patent: 5724297 (1998-03-01), Noda et al.
patent: 5748542 (1998-05-01), Zheng et al.
patent: 5978297 (1999-11-01), Ingalls
patent: 08083487 (1996-03-01), None
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nguyen Hien
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