Temperature-dependent refresh cycle for DRAM

Details Temperature-dependent refresh cycle for DRAM Temperature-dependent refresh cycle for DRAM

2005-02-01

2005-02-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S212000, C365S222000

Reexamination Certificate

active

06850448

ABSTRACT:
A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a temperature-dependent reference voltage source. A capacitor's first and second terminals are connected respectively to the temperature-independent current source, and the temperature-independent voltage source. The capacitor's first terminal is connected to a first input terminal of a comparator. The comparator's second input is connected to the temperature-dependent reference voltage source. The comparator is configured to output a refresh signal in response to a difference between voltages present at the first and second inputs thereof.

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