Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-07-06
2001-03-20
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189090, C365S185220
Reexamination Certificate
active
06205074
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and, more particularly, to a method for generating a bias voltage during APDE verify in flash electrically erasable programmable read-only memory (flash EEPROM) devices.
BACKGROUND OF THE INVENTION
A flash memory is a storage device that is capable of retaining stored information in the absence of continuous power. The information is stored in a plurality of flash transistors that are electrically connected and formed on a silicon substrate. A flash transistor is typically referred to as a cell and includes a source, a drain, a floating gate and a control gate. Flash memory devices are formed by rows and columns of flash transistors that form a flash transistor array. As known in the art, the control gates of the cells are electrically connected with a respective wordline and the drains of the cells are electrically connected with a respective bitline. The source of each cell is electrically connected with a common source line.
The information stored in each particular cell represents a binary one or zero, as known in the art. To perform a program, read or erase operation of a particular cell in the array, a respective voltage is applied to a predetermined wordline, bitline and sourceline. By applying the voltages to a select bitline column and a select wordline row, an individual cell can be read or programmed.
To program a respective cell, the control gate and the drain of the cell are raised to respective predetermined programming voltages and the source is grounded. When the programming voltages are placed on the control gate and the drain, hot electrons are generated that are injected onto the floating gate where they are trapped forming a negative charge. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection in the semiconductor industry. When the programming voltages are removed, the negative charge on the floating gate is maintained, thereby raising the threshold voltage of the cell. The threshold voltage is used when the cell is read to determine if it is in a charged (programmed) or an uncharged (un-programmed) state.
Cells are read by applying a predetermined voltage to the control gate and the drain, grounding the source of the cell and then sensing the current in the bitline. If the cell is programmed, the threshold voltage will be relatively high and the bitline current will be zero or at least relatively low when a read voltage is applied between the control gate and the source of the cell. If the cell is erased, the threshold voltage will be relatively low and the bitline current will be relatively high when the same read voltage is applied.
In contrast to the programming procedure, flash memory devices are typically bulk-erased, so that all of the cells in a memory sector are simultaneously erased. A memory sector describes the number of wordlines and bitlines in the array and can be formed to include 512 wordlines and 1024 bitlines in a 64-kbyte array. Erasing memory sectors can be performed in several ways involving the application of a set of predetermined voltages to the common sourceline, the bitlines and the wordlines. This causes electron tunneling from the floating gate to the source through Fowler-Nordheim (F-N) tunneling, which removes the negative charge from the floating gate of the cells in the memory sector.
Cells are typically erased by application of an erase pulse to the memory sector targeted for erasure for a predetermined time. Ideally, each cell in the memory sector requires the same amount of time to remove electrons from the floating gate. In reality, erase times among the cells within the memory sector vary and some of the cells subjected to the erase pulse may become over-erased. The threshold voltage of an over-erased cell is lowered to the point that it can cause excessive leakage current in the bitline. Excessive leakage current can prevent proper reading of programmed cells in the bitline of the memory sector.
It is known in the art that to correct for excessive leakage current, the bitlines are verified during an Automatic Program Disturb Erase Verify (APDEV) operation that occurs automatically as part of an Automatic Program Disturb Erase (APDE) operation. The APDEV operation verifies that each bitline in a particular sector does not contribute excessive leakage current above a predetermined reference current and takes corrective action if necessary. The predetermined reference current is obtained by sensing the bitlines of at least one reference cell.
During the APDEV operation, a bias voltage is applied to all the wordlines in the sector and each bitline in the sector is sequentially sensed for current above the predetermined reference current. The bias voltage is also applied to the wordlines of the reference cells to obtain the predetermined reference current. If the bitline current is above the reference current, a stress operation is performed on all the cells in the bitline. A stress operation is known in the art as a soft program that mainly affects the over-erased cells by raising their threshold voltage. After the stress operation, the bitline current is sensed again and the stress operation is repeated if necessary until the current sensed on the bitline during the APDEV operation is below the reference current.
The leakage current generated when the bias voltage is applied to the cells varies with the operating temperature of the flash memory. A known problem occurs during the erase operation when the temperature variations of the flash memory are enough to disturb the accuracy of the leakage current sensing. When the operating temperature varies, the leakage current of the cells in the bitlines varies to a greater degree than the leakage current of the reference cells. The non-uniform variations in the leakage currents may cause an erroneous bitline current or an erroneous predetermined reference current during the APDEV operation.
If the leakage current of the cells on the bitlines is erroneously too high, or if the reference current is erroneously too low, the stress and APDEV operations will be repeated. Repetition of the stress and APDEV operations undesirably lengthens the duration of the erase operation. In addition, temperature variations that allow the leakage current in the bitlines to be erroneously determined acceptable, causes erroneous results when the programmed cells in the bitlines are later read.
For the foregoing reasons, a need exists to temperature compensate the generation of the leakage current and the predetermined reference leakage current as the operating temperature of the flash memory varies.
SUMMARY OF THE INVENTION
The present invention discloses methods and systems of generating a bias voltage during an APDEV operation in a memory device that, in the preferred embodiment, is a flash memory. The preferred flash memory includes a charge share circuit and a temperature-compensated bias generator circuit that are electrically connected to at least one pass gate. In addition, the charge share circuit is electrically connected with the temperature-compensated bias generator circuit. The pass gates are electrically connected with at least one wordline located in a memory sector of the flash memory.
During the APDEV operation, the charge share circuit generates a first predetermined voltage that is directed to the wordlines through the pass gates. After the charge share circuit charges the wordlines to a base voltage, the temperature-compensated bias generator circuit generates a second predetermined voltage that is directed with the pass gates to the wordlines. The second predetermined voltage is temperature-compensated and charges the wordlines to a bias voltage.
The second predetermined voltage is equal to the bias voltage that is needed to verify the bitlines in a respective memory sector at the present operating temperature of the flash memory. Verification of the bitlines involves charging the wordlines of a respective memory sector to the bias voltage and
Van Buskirk Michael A.
Venkatesh Bhimachar
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Nguyen Tan T.
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