Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2003-04-03
2004-04-20
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C216S059000, C216S060000, C216S084000, C216S085000, C216S037000
Reexamination Certificate
active
06723650
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to IC metrology and defect inspection techniques used in the inspection of defects in WIP (work-in-progress) wafers during the fabrication of semiconductor integrated circuits. More particularly, the present invention relates to preparation of a TEM (transmission electron microscopy) sample for IC defect inspection by providing a transparent protective coating over a defect on a sidewall in a first cross-section opening prior to milling a second cross-section opening in the sample on the opposite side of the defect, in order to prevent metal particle contamination of the defect.
BACKGROUND OF THE INVENTION
The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
Throughout the IC fabrication process, the WIP wafers must be frequently tested to monitor the physical and electrical properties of the devices being fabricated thereon. Wafer testing is carried out on sample wafers using a measurement tool and equipment to analyze the data. These testing tools and equipment may use physical methods that allow ions, electrons and/or electromagnetic radiation to interact with the device features and then examine the secondary particles and/or radiations that are produced. The information obtained from the interaction of the particles and/or radiation with a region of interest in the device is then used to deduce the properties of the materials in the region of interest. The information reveals the presence of defects, which are characteristics of the wafer or results of the wafer fabrication process that cause nonconformance to the specified wafer requirements.
Some of the techniques widely used to inspect defects in wafers throughout IC fabrication include Scanning Electron Microscopy (SEM), Transmission Electron Microscopy (TEM), and Auger Electron Spectrometery (AES). The TEM method is particularly popular since transmission of electrons through a sample allows obtaining information via diffraction mechanisms which, in turn, provides information concerning longer-range order. TEM is a valuable tool used to quantify very small features on a wafer. For example, TEM can be used to image, on an atomic scale, silicon crystal point defects such as single dislocations that are introduced into an active junction by ion implant and lead to junction leakage. In TEM, a beam of electrons is transmitted through an ultra thin (about 10-100 nm thick) slice of the sample. Based on such factors as electron wavelength, accelerating voltage and specimen thickness, an image is formed and magnified on a screen with a resolution of about 2 angstroms. Unfortunately, sample preparation for TEM analysis is difficult and time-consuming since the thickness of the sample must not exceed about 100 nm to yield meaningful results.
Several techniques have been used to prepare TEM samples that do not exceed the typical 100 nm thickness limit for optimum imaging. Since the early 1990s, sample cross-sections have been prepared using a milling technique which is carried out by Focused Ion Beam (FIB) technology. The FIB technique uses an ion beam made of gallium ions that are focused through a set of lenses into a small spot on the wafer. At the point where they strike the wafer, the gallium ions are ejected into a vacuum, creating a small void, the shape and depth of which is precisely controlled, in the sample.
The FIB milling technique is illustrated in
FIGS. 1 and 2
. According to the FIB milling technique, a first cross-section void
16
is initially cut in the top surface
14
of a wafer section
10
, adjacent to a defect
20
to be subsequently imaged using TEM, using a focused ion beam
24
ejected from an FIB apparatus
23
. The defect
20
appears in a sidewall
18
of the first cross-section void
16
. A metal cutting line
22
deposited on the top surface
14
serves as a guide along which the wafer section
10
is to be subsequently cut for preparation of the TEM sample
19
which contains the defect
20
. The metal cutting line
22
, which is typically platinum or tungsten, is deposited using any appropriate metal deposition method, such as by use of the FIB apparatus
23
using a low beam intensity.
As shown in
FIG. 2
, the focused ion beam
24
cuts the wafer section
10
along the metal cutting line
22
to form a second cross-section void
26
, leaving the TEM sample
19
which contains the defect
20
separating the first cross-section void
16
and the second cross-section void
26
. The focused ion beam
24
cuts the TEM sample
19
to a thickness of typically less than 100 nm. Finally, the TEM sample
19
is subjected to a transmission electron microscopy (TEM) technique in which electrons are transmitted through the TEM sample
19
for imaging of the defect
20
. Based on such factors as electron wavelength, accelerating voltage and specimen thickness, an image of the defect
20
is formed and magnified on a screen (not shown) to reveal information such as the type and dimension of the defect
20
. This information is used by IC manufacturing personnel to make corrective measures to the various process parameters likely to have caused the defect in an effort to ensure product performance and quality.
One of the drawbacks associated with the conventional FIB milling technique is that as the focused ion beam
24
cuts the wafer section
10
along the metal cutting line
22
to form the second cross-section void
26
, metal particles frequently are dislodged from the metal cutting line
22
and deposited on the exposed defect
20
in the TEM sample
19
. This adversely affects the quality and accuracy of the TEM image of the defect
20
that is generated during the subsequent TEM step. Accordingly, a technique is needed for protecting the defect from deposit of metal particles thereon during the milling operation in order to achieve a clear, accurate and high-quality TEM image of the defect.
Accordingly, an object of the present invention is to provide a technique for preserving the quality of a defe
Fourson George
Maldonado Julio J.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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