Technology partitioning for advanced flip-chip packaging

Details Technology partitioning for advanced flip-chip packaging Technology partitioning for advanced flip-chip packaging

2006-12-05

2006-12-05

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

active

07144759

ABSTRACT:
Packaging processes and structures provide thin-film interconnects for high performance signal transmission of high frequency signals. The thin-film interconnects can be formed on a carrier that is at least partly removed for formation of terminals such as a BGA connected to the thin-film interconnects. Removal of the carrier can leave a frame for handling of the thin-film interconnects during subsequent processing. The thin film interconnects can be used to route signals to external terminals, between dies, or between functional units within a die. This allows the dies to contain fewer routing layers and allows configuration of a device such as an ASIC during packaging. A coarser pitch interconnect structure can be fabricated on the carrier using different technology for power and ground management and/or in a core that attaches to the thin-film package structure.

REFERENCES:
patent: 6759268 (2004-07-01), Akagawa

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