Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-27
2007-11-27
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C430S005000, C430S394000, C438S014000
Reexamination Certificate
active
10904225
ABSTRACT:
A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
REFERENCES:
patent: 5535134 (1996-07-01), Cohn et al.
patent: 6099582 (2000-08-01), Haruki
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6378113 (2002-04-01), Levitsky et al.
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6756242 (2004-06-01), Regan
patent: 6818389 (2004-11-01), Fritze et al.
patent: 6901577 (2005-05-01), Kotani et al.
patent: 6925627 (2005-08-01), Longway et al.
patent: 6973636 (2005-12-01), Shin et al.
patent: 7007258 (2006-02-01), Li
patent: 7039881 (2006-05-01), Regan
patent: 7096446 (2006-08-01), Karniewicz
patent: 7137092 (2006-11-01), Maeda
patent: 7155689 (2006-12-01), Pierrat et al.
patent: 2004/0185351 (2004-09-01), Cote et al.
patent: 2005/0251771 (2005-11-01), Robles
patent: 2006/0085773 (2006-04-01), Zhang
patent: 2006/0121715 (2006-06-01), Chang et al.
patent: 2006/0195809 (2006-08-01), Cohn et al.
Chen et al., “Hierarchical dummy fill for process uniformity”; Jan. 30-Feb. 2, 2001; Design Automation Conference, Proceedings of the ASP-DAC 2001. Asia and South Pacific; pp. 139-144.
Carlson, E.C. et al., “A Scanline Data Structure Processor for VLSI Geometry Checking,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 6, Issue 5, Sep. 1987, pp. 780-794.
Allen Robert J.
Endicott Cam V.
Heng Fook-Luen
Hibbeler Jason D.
McCullen Kevin W.
Chiang Jack
Hoffman Warnick & D'Alessandro LLC
Kotulak Richard M.
Rossoshek Helen
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