Technology mapping technique for fracturable logic elements

Details Technology mapping technique for fracturable logic elements Technology mapping technique for fracturable logic elements

2006-08-29

2006-08-29

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07100141

ABSTRACT:
A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.

REFERENCES:
patent: 5119313 (1992-06-01), Shaw et al.
patent: 5150309 (1992-09-01), Shaw et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5594657 (1997-01-01), Cantone et al.
patent: 5610829 (1997-03-01), Trimberger
patent: 5648912 (1997-07-01), Narayanan et al.
patent: 5754824 (1998-05-01), Damiano et al.
patent: 5926803 (1999-07-01), Kitano
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6212670 (2001-04-01), Kaviani
patent: 6311316 (2001-10-01), Huggins et al.
patent: 6321366 (2001-11-01), Tseng et al.
patent: 6389379 (2002-05-01), Lin et al.
patent: 6415425 (2002-07-01), Chaudhary et al.
patent: 6519755 (2003-02-01), Anderson
patent: 6590415 (2003-07-01), Agrawal et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 6760899 (2004-07-01), Young et al.
patent: 6785873 (2004-08-01), Tseng
patent: 6851101 (2005-02-01), Kong et al.
patent: 6952816 (2005-10-01), Gupta et al.
patent: 2003/0200520 (2003-10-01), Huggins et al.
patent: 2004/0210857 (2004-10-01), Srinivasan
patent: 2005/0039155 (2005-02-01), New
patent: 2005/0091630 (2005-04-01), Madurawe
Lu et al., “Tradeoff Literals Against Support for Logic Synthesis of LUT-based FPGAs”, IEE Proceedings of Computers and Digital Techniques, vol. 143, No. 2, Mar. 1996, pp. 111-119.
Cong et al., “Boolean Matchnig for LUT-based Logic Blocks with Applications to Architecture Evaluation and Technology Mapping”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 9, Sep. 2001, pp. 1077-1090.
de Lima et al., “A Tool for Analysis of Universal Logic Gates Functionality”, Proceedings of XII Symposium on Integrated Circuits and Systems, Sep. 29, 1999, pp. 184-187.
Murgai et al., “Cube-packing and Two-level Minimization”, IEEE/ACM International Conference on Computer-Aided Design, Nov. 7, 1993, pp. 115-122.
Reese et al., “A Coarse-Grain Phased Logic CPU”, Proceedings of Nineth International Symposium on Asynchronous Circuits and Systems, May 12, 2003, pp. 2-13.
Chaddha et al., “Constrained and Recursive Hierarchical Table-Lookup Vector Quantization”, Proceedings of Data Compression Conference, Mar. 31, 1996, pp. 220-229.
Cong, J. et al., “FlowMap: An Optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,” IEEE Trans. Computer-Aided Design, vol. 13, pp. 1-12, Jan. 1994.
Cong, J. et al., “Simultaneous depth and area minimization in LUT-based FPGA mapping,” Proc. ACM 3rd Int. Symp. FPGA, pp. 68-74, Feb. 1995.
Francis, R.J. et al., “Chortle-crf: Fast technology mapping for lookup table-based FPGA's,” Proc. 28th ACM/IEEE Design Automation Conf., 1991, pp. 613-619.
Murgai, R. et al., “Improved logic synthesis algorithms for table loop up architectures,” Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1991, pp. 564-567.
Farrahi, A. et al., “Complexity of the lookup-table minimization problem for FPGA technology mapping,” IEEE Trans. Computer-Aided Design, vol. 13, pp. 1319-1332, Nov. 1994.
Cong, J. et al., “Combinational logic synthesis for LUT based field programmable gate arrays,” ACM Trans. Des. Auto., Electron Syst., vol. 1, No. 2, pp. 145-204, 1996.
Cong, J. et al., Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs,: Proc. IEEE Int. Conf., Computer-Aided Design, Nov. 1993, pp. 110-114.
Chowdhary, A. et al., “General modeling and technology mapping technique for LUT-based FPGAs,” Proc. 5th ACM/SIGDA Int. Symp. FPGAs, pp. 43-49, Feb. 1997.

Affiliated with

Also associated with

Rating

Technology mapping technique for fracturable logic elements does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Technology mapping technique for fracturable logic elements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technology mapping technique for fracturable logic elements will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3660591