Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-03
2002-02-26
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S388000, C257S412000
Reexamination Certificate
active
06351016
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming simultaneously a tungsten polycide gate and an improved buried contact without a trench in the fabrication of integrated circuits.
(2) Description of the Prior Art
FIGS. 1-4
illustrate a typical buried contact process of the prior art.
FIG. 1
illustrates a partially completed integrated circuit device. Isolation regions, such as shallow trench isolation (STI)
12
, are formed in and on the semiconductor substrate
10
. A gate oxide layer
14
is grown upon the surface of the substrate. Typically, a so-called “split poly” process is used wherein a first layer of polysilicon
16
is deposited over the gate oxide layer to protect the gate oxide from the photoresist process. A layer of photoresist is coated over the polysilicon layer
16
and patterned to form the photoresist mask
20
.
The polysilicon and gate oxide layers are etched away where they are not covered by the photoresist mask to form an opening where the buried contact is to be formed. As illustrated in
FIG. 2
, ions
22
are implanted into the semiconductor substrate through the opening to form the buried contact junction
24
.
Referring now to
FIG. 3
, the second layer of the split poly
26
is deposited over the first polysilicon layer and within the opening. A tungsten silicide layer
28
is deposited over the second polysilicon layer. A second photoresist mask
30
is formed over the substrate.
Referring now to
FIG. 4
, the tungsten silicide layer, two polysilicon layers, and gate oxide layer
28
,
26
,
16
, and
14
are etched to form gate electrode
32
and polysilicon interconnection line
34
. Source/drain regions
36
are formed.
As device dimensions and cell size continue to decrease for high density and improved performance in integrated circuits, there is a growing demand for lower junction leakage and lower contact resistance. However, the contact resistance and junction leakage will increase in the conventional buried contact process if there is misalignment of the photoresist mask during polysilicon etching.
FIG. 5
illustrates the case in which the photoresist mask
30
is shifted to the left. Buried contact trench
35
is formed. This causes an increase in both contact resistance and leakage current.
FIG. 6
illustrates the case in which the photoresist mask is shifted to the right. A disconnection gap
37
is left between the buried contact
24
and the source/drain region
36
. This increases contact resistance by causing a high series resistance.
A number of patents disclose methods for improving a device in which a buried contact trench has been formed. For example, U.S. Pat. No. 5,525,552 to J. M. Huang teaches the use of a low dielectric constant spacer to provide better immunity of the buried contact trench. U.S. Pat. No. 5,607,881 also to J. M. Huang teaches linking the buried contact junction and the source junction by an extra high dosage N+ implant to overcome the disadvantages of a buried contact trench. U.S. Pat. No. 5,668,051 to Chen et al teaches a thin polysilicon layer within the buried contact trench. U.S. Pat. No. 5,652,152 to Pan et al discloses the use of a PSG spacer to solve the buried contact trench problem.
Other patents teach methods to avoid forming a buried contact trench. For example, U.S. Pat. No. 5,494,848 to H. W. Chin teaches the use of a reverse tone oversized buried contact mask to prevent formation of a buried contact trench. U.S. Pat. No. 5,654,231 to M. S. Liang et al teaches the use of sidewall spacers to prevent the formation of a buried contact trench in DRAM technology. Co-pending U.S. patent application Ser. No. 09/034,927 to K. C. Huang et al, now U.S. Pat. No. 6,080,647 issued on Jun. 27, 2000, teaches forming a buried contact after formation of the gate electrode and interconnection lines and selective deposition of tungsten over the buried contact and gate electrode.
Still other patents teach other buried contact processes. For example, U.S. Pat. No. 5,543,362 to Wu teaches a process in which a silicide layer is deposited over the buried contact region followed by a polysilicon layer and topped with a second silicide layer. U.S. Pat. No. 5,162,259 to Kolar et al teaches forming a silicide over the buried contact region and depositing polysilicon overlying the silicide.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming buried contact junctions.
Another object of the present invention is to provide a method of forming buried contact junctions which avoids the formation of a trench caused by mask misalignment.
Another object of the invention is to provide a method of forming buried contact junctions which avoids the formation of a disconnection gap caused by mask misalignment.
Yet another object of the present invention is to provide a method of forming buried contact junctions in which only a single deposition of polysilicon is required.
A further object of the invention is to provide a method of forming buried contact junctions in which the buried contact is connected and the polycide gate and interconnection lines are formed simultaneously.
A still further object is to provide a method of forming buried contact junctions which avoids the formation of a trench caused by mask misalignment and in which only a single deposition of polysilicon is required.
A still further object is to provide a method of forming buried contact junctions which avoids the formation of a trench caused by mask misalignment, in which only a single deposition of polysilicon is required, and in which the buried contact is connected and the polycide gate and interconnection lines are formed simultaneously.
In accordance with the objects of this invention a new method of forming an improved buried contact junction is achieved. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a hard mask layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer, such as tungsten or tungsten silicide, is deposited over lying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
Also, in accordance with the objects of this invention, a new integrated circuit device having a buried contact junction is described. A buried contact junction lies within a semiconductor substrate having a tungsten or tungsten silicide contact layer thereover. A polycide gate electrode lies on the surface of the semiconductor substrate having source and drain regions within the semiconductor substrate surrounding the polycide gate electrode wherein one of the source and drain regions contacts the buried contact junction. An insulating layer overlies the said polycide gate electrode, the tungsten contact layer, and the source and drain regions. A patterned conducting layer overlies the insulating layer and extends through an opening in the insulating layer to another one of the un
Huang Jenn-Ming
Huang Kuo-Ching
Wuu Shou-Gwo
Yaung Dun-Nian
Ackerman Stephen B.
Pike Rosemary L. S.
Quach T. N.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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