Technology dependent transformations for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07039882

ABSTRACT:
The present invention pertains to automated technology dependent transformations for Silicon-On-Insulator (SOI) in the digital design synthesis, the transformations include the steps of receiving input design specification in the form of technology independent specification or interconnected library of standard-cells; performing the technology dependent transformations in the digital design synthesis, resulting in interconnected SOI standard-cells from a SOI target library accounting for floating body effects, including floating body effects affecting delays over long periods of simulation time or testing over long times on fabricated SOI library cells, or SOI transistor level representations, transistor sizing and evaluating the standard-cell mapping and transistor-level representation for all or portion of the input design specification iteratively to meet delay and power constraints for SOI.

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Shahriari, M. Et al. “A gate level timing model for SOI circuits”, IEEE, 2001. pp. 795-798.
Tu, Robert, et al., “Simulation of floating body effect in SOI circuits using BSIM3SOI”, VSI Technology, Systems, and Applications, 1997, p. 339-342.
Giovanni De Micheli, “Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits”, IEEE Transactions in Computer-aided-Design vol. CAD-6 No. 5 Sep. 1987 pp. 751-765.

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