Techniques to perform error detection

Details Techniques to perform error detection Techniques to perform error detection

2004-09-23

2009-06-09

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C702S189000

Reexamination Certificate

active

07546512

ABSTRACT:
Method and apparatus to perform cyclic redundancy check computations for error detection are described wherein a first stage includes a first set of computation elements, a first multiplexer and a second multiplexer. A latch is connected to the first stage. A second stage is connected to the latch and the second stage includes a second set of computation elements and a third multiplexer. The first stage and the second stage perform cyclic redundancy check computations for a packet, with the first set of computation elements performing cyclic redundancy check computations for a first set of bytes of input data from the packet, and the second set of computation elements performing cyclic redundancy check computations for a second set of bytes of input data from the packet. Other embodiments are described and claimed.

REFERENCES:
patent: 2002/0053059 (2002-05-01), Hara et al.
patent: 2003/0159101 (2003-08-01), Hyland et al.
patent: 2005/0172205 (2005-08-01), Lin et al.

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