Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-02-13
2009-06-30
Nguyen, Hiep T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07555608
ABSTRACT:
Techniques are described herein that may be used to invalidate all entries in a table. For example, the table may be a flow cache. For example, an expiry time may be associated with one or more entries in the table. The expiry time of an entry may be initially set to the sum of the system time, the expiry time of the protocol associated with the entry, and a global time variable. To check if the entry is expired at any time, the current system time may be added to the global time variable and if the result is greater than the expiry time in the entry, then the entry is expired. To invalidate all the entries, the global time variable may be incremented by a large amount which may equal the maximum expiry time of all protocols. This may cause all entries to expire. New entries may be added using the new incremented value of the global time variable and will hence not expire.
REFERENCES:
patent: 2007/0156966 (2007-07-01), Sundarrajan et al.
Kumar Alok
Naik Uday
Vipat Harshawardhan
Caven & Aghevli LLC
Intel Corporation
Nguyen Hiep T
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