Techniques to control signal phase

Details Techniques to control signal phase Techniques to control signal phase

2002-07-17

2004-12-28

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S157000, C327S162000, C327S294000, C327S299000

Reexamination Certificate

active

06836167

ABSTRACT:

1. Field
The subject matter herein generally relates to the field of phase locked loops.
2. Description of Related Art
Phase locked loop (PLL) devices can be used to match the phase of a clock signal with that of an input signal.
FIG. 1
depicts an example PLL device. The clock generator
110
outputs a clock signal (shown as CLK). A phase comparator
120
compares the phase of an input signal (shown as INPUT) with that of signal CLK. The phase comparator
120
may output an UP or a DN pulse. The UP and DN pulses may control the charge pump
130
. When signal CLK is behind the signal INPUT, phase comparator
120
outputs an UP pulse to charge pump
130
to instruct the charge pump
130
to provide more charge to the clock generator
110
to increase the speed of the signal CLK (over time) to match the phase of CLK with that of INPUT. Conversely, when the signal CLK is ahead of the signal INPUT, phase comparator
120
outputs a DN pulse to charge pump
130
to instruct charge pump
130
to remove charge from the clock generator
110
to decrease the speed of the signal CLK (over time). The charge pump
130
may add or remove an amount of charge in proportion to the width of respective UP and DN pulses.
Phase comparator
120
may output UP and DN pulses having fixed duration active states. For example,
FIG. 2
depicts sample waveforms of UP and DN pulses having fixed duration active states. Use of fixed width UP and DN pulses may not accurately match the phase of the signal CLK with that of the signal INPUT.


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