Magnetic ram cell with amplification circuitry and MRAM...

Details Magnetic ram cell with amplification circuitry and MRAM... Magnetic ram cell with amplification circuitry and MRAM...

2002-02-20

2004-12-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S072000, C365S173000, C365S189090, C365S189110

Reexamination Certificate

active

06829160

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to magnetic memory systems, and more particularly to a method and system for providing a magnetic memory cell and a memory array including the magnetic memory cells.
BACKGROUND OF THE INVENTION
Magnetic memories are often used in storing data. One type of memory currently of interest utilizes magnetic tunneling junctions in the memory cells. A magnetic tunneling junction typically includes two ferromagnetic layers separated by a thin insulating layer. The insulating layer is thin enough to allow charge carriers to tunnel between the ferromagnetic layers. The resistance of the magnetic tunneling junction depends upon the orientation of the magnetic tunneling junctions.
FIG. 1
depicts a conventional magnetic memory cell
10
as used in a conventional magnetic memory. The conventional memory cell
10
is coupled with a voltage supply line
20
and receives a current I
r
18
during reading. The conventional memory cell
10
includes a magnetic tunneling junction
12
and a transistor
14
. The magnetic tunneling junction
12
is represented by a resistor. The magnetic tunneling junction
12
is coupled to the drain of the transistor
14
. The source of the transistor
14
is coupled to ground. The state of the magnetic tunneling junction
12
, and thus the data stored by the conventional memory cell
10
is sensed by detecting the voltage at output
16
. The output
16
is coupled to the magnetic tunneling junction
12
of the conventional memory cell
10
.
FIG. 2
depicts a conventional memory array
30
using the conventional memory cell
10
. The conventional array
30
is shown as including four conventional memory cells
10
. The memory cells
10
are coupled to reading/writing column selection
32
via bit lines
34
and
36
and to row selection
50
via word lines
52
and
54
. The bit lines are coupled to the magnetic tunneling junctions
12
, while the word lines
52
and
54
are coupled to the gates of the transistors
14
. Also depicted are digit lines
44
and
46
which carry current that applies a field to the appropriate conventional memory cells
10
during writing. The reading/writing column selection
32
is coupled to write current source
38
and read current source
40
which are coupled to a line
42
coupled to a supply voltage VDD
48
. Also shown are current source I
W
38
and I
r
40
used in writing and reading, respectively, to the conventional memory cells
10
. Also depicted are transistors
58
and
60
that are controlled using control line
62
.
In order to write to the conventional memory cell
10
, the write current I
W
38
is applied to the bit line
34
or
36
selected by the writing/reading column selection
32
. The read current I
r
40
is not applied. Both word lines
52
and
54
are disabled. The transistors
14
in all memory cells are disabled. In addition, one of the digit lines
44
or
46
selected carries a current used to write to the selected conventional memory cell
10
. The combination of the current in a digit line
44
or
46
and the current in a bit line
34
or
36
will write to the desired conventional memory cell
10
. Depending upon the data written to the conventional memory cell
10
, the magnetic tunneling junction will have a high resistance or a low resistance.
When reading from a conventional cell
10
in the conventional memory array
30
, the write current I
W
38
is disabled and the transistors
58
and
60
are turned off by controlling the control signal through the control line
62
. The read current I
r
,
40
is applied instead. The memory cell
10
selected to be read is determined by the row selection and column selection
32
. The transistors
14
in the selected cell are on. The output voltage is read at the output line
56
. For example, assuming that the resistance of the magnetic tunneling junction in a low (ferromagnetic layers polarized parallel) state is twenty kilo-ohms, that the magnetoresistance ratio is twenty percent, and that a read current used is ten micro-amps. In such a case, the output voltage would either be 240 mV or 200 mV. Thus, there is a forty millivolt difference in the signals output for different states of the conventional magnetic memory cell
10
.
Although the conventional memory array
30
and the conventional memory cells
10
function, one of ordinary skill in the art will readily recognize that the difference in the signals output by the conventional memory cells
10
is relatively small. The difference in output signals between the two states of the conventional memory cell
10
is on the order of tens of millivolts. The output signals are typically on the order of a few hundred millivolts. As a result, the conventional memory cells
10
and the conventional memory array may be subject to errors.
Accordingly, what is needed is a system and method for providing a magnetic memory cell having an improved signal. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a magnetic random access memory (MRAM) cell and a memory array formed from the MRAM cells. The MRAM cell includes a magnetic tunneling junction and a transistor. The magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The transistor has a source, a drain and a gate. The gate of the transistor is coupled to a first end of the magnetic tunneling junction. The source of the transistor is coupled to a second end the magnetic tunneling junction. The drain of the transistor is coupled with an output for reading the magnetic memory cell.
According to the system and method disclosed herein, the present invention provides a magnetic memory having an amplified output signal.


REFERENCES:
patent: 6201259 (2001-03-01), Sato et al.
patent: 6512690 (2003-01-01), Qi et al.
patent: 11204854 (1999-07-01), None

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