Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2008-04-22
2008-04-22
Fan, Chieh M. (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C341S068000, C375S219000
Reexamination Certificate
active
07362839
ABSTRACT:
Techniques to modify bias levels of a limiting amplifier based on a transition measurement and measurements before and after the transition.
REFERENCES:
patent: 6002723 (1999-12-01), Chethik
patent: 6737995 (2004-05-01), Ng et al.
patent: 6885209 (2005-04-01), Mak et al.
patent: 2003/0081667 (2003-05-01), Camnitz et al.
patent: 2003/0193423 (2003-10-01), Ng et al.
patent: 2004/0036494 (2004-02-01), Mak et al.
Hansryd, Jonas et al., “Prescaled Clock Recovery Based on Small Timing Misalignment of Data Pulses,” Journal of Lightwave Technology, vol. 19, No. 1, pp. 105-113, Jan. 2001.
European Patent Office, International Search Report and Written Opinion for International Application No. PCT/US2005/016555, 12 pages, Aug. 8, 2005.
Goth Bjarke
Joergensen Tore Sejr
Caven & Aghevli LLC
Fan Chieh M.
Intel Corporation
Joseph Jaison
LandOfFree
Techniques to adjust vertical offset does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques to adjust vertical offset, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques to adjust vertical offset will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2765906