Static information storage and retrieval – Read/write circuit – Including signal clamping
Reexamination Certificate
1999-09-21
2001-01-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal clamping
C365S230060
Reexamination Certificate
active
06181611
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits, and more specifically to high voltage isolation circuitry for a memory integrated circuit.
Memory integrated circuits such as DRAMs, SRAMs, EPROMs, EEPROMs, and Flash memories are used in many applications such as computers, networking, and telecommunications. Consumers continue to demand greater performance in their electronic products. For example, higher speed computers will provide higher speed graphics for multimedia applications or development. Higher speed internet web servers will lead to greater on-line commerce including on-line stock trading, book sales, auctions, and grocery shopping, just to name a few example. Higher performance memory integrated circuits will improve the performance of the products in which they are incorporated.
In particular, the speed of a memory integrated circuit depends on the internal propagation delays of signals within the circuit. An array of memory cells in a memory circuit is typically organized by rows and columns. By providing an address to the row decoders, a row decoder selects a particular row. A speed path propagation delay is determined in part by the time it takes for a decoder to access or drive a particular row. Furthermore, it is important that the voltages selected to interface with the array and other circuitry provides for reliable and proper operation of the integrated circuit.
As can be seen, techniques and circuitry for improving the performance of memory integrated circuits are needed.
SUMMARY OF THE INVENTION
The present invention provides techniques and circuitry for improving the performance of a memory integrated circuit. More specifically, a pass gate isolation circuit of the present invention provides voltages to isolation pass gates (which couple the row decoders to the word lines of a memory array) that allow higher speed access of rows in the memory array.
When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage at its output. Subsequently, the output becomes a steady state high voltage maintained by a high voltage keeper circuit and a voltage clamp circuit.
When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and high voltage isolation of the row decoders.
The techniques and circuitry of the present invention allow the design and fabrication of higher performance integrated circuits. Greater reliability and low power consumption are also provided.
In a specific embodiment, the present invention is an integrated circuit including a first transistor connected to an output node; a second transistor connected between the output node and a first supple voltage, where a gate of the second transistor is connected to the first transistor; and a third transistor coupled between the gate of the second transistor and a second supply voltage. Furthermore, a substrate connection of the first transistor and second transistor may be coupled to the output node. A further embodiment of the invention may include a high voltage keeper circuit to provide a high voltage to the output node; and a voltage clamp circuit coupled to clamp a high voltage at the output node.
In another embodiment, the present invention is an integrated circuit memory including an array of memory cells arranged in rows and columns, where the rows of memory cells are associated with a plurality of word lines. There are a plurality of row decoders to drive the plurality of word lines. There are a plurality of isolation pass gate devices connected between the plurality of row decoders and plurality of word lines of the array of memory cells. There is a pass gate isolation circuit to provide voltages to control electrodes of the plurality of isolation pass gate devices. The pass gate isolation circuit dynamically couples to the control electrodes a first high voltage level during a first period of a first operational mode, and provides a second high voltage level during a second period of the first operational mode.
In a further embodiment, the present invention includes a method of operating an integrated circuit including in a first mode, a first voltage level is provided to an isolation device to isolate a high voltage on a word line form being drained by a row decoder coupled to the word line. In a second mode, a second voltage level is dyanmically coupled to the isolation device to permit transfer of a signal the row decoder to the word line. Furthermore, in the second mode, a third voltage level is maintained to the isolation device in a steady state.
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Le Vu A.
Townsend and Townsend / and Crew LLP
Winbond Electronics Corporation
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