Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2004-12-01
2008-09-02
Shin, Christopher (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S019000, C710S310000, C710S030000, C709S234000
Reexamination Certificate
active
07421522
ABSTRACT:
Techniques for transmitting and receiving FIFO status signals on a hard intellectual property (HIP) block of a programmable logic integrated circuit are provided. The FIFO status signals are demultiplexed after being received in the HIP block and then stored in a per port context. The FIFO status signals are retrieved from a storage block in a per port context and transmitted out of the HIP block through a multiplexer. The demultiplexing and multiplexing reduces the number of input and output ports that are needed to transmit the status signals into and out of the HIP block, yet providing the necessary status throughput for a full-rate SPI4.2 status channel implementation.
REFERENCES:
patent: 4766536 (1988-08-01), Wilson et al.
patent: 5521918 (1996-05-01), Kim
patent: 5768560 (1998-06-01), Lieberman et al.
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 6091262 (2000-07-01), New
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6242945 (2001-06-01), New
patent: 6324596 (2001-11-01), Houg
patent: 6363211 (2002-03-01), Kanota et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6526563 (2003-02-01), Baxter
patent: 6982989 (2006-01-01), Park et al.
“Atlantic Interface,” Altera Functional Specification 13, version 3.0, Altera Corporation San Jose, CA (Jun. 2002).
“FPGAs & FPSCs from Lattice: ORSPI4,” product information from http://www.latticesemi.com, Lattice Semiconductor Corporation Hillsboro, OR (2003).
“ORCA® ORSPI4 Dual SPI4 Interface and High Speed Serdes FPSC,” product information Lattice Semiconductor Corporation Hillsboro, OR (2004).
System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices, Optical Internetworking Forum Implementation Agreement : OIF-SPI4-02.0 (Jan. 2001).
Altera Corporation
Shin Christopher
Townsend and Townsend / and Crew LLP
LandOfFree
Techniques for transmitting and receiving SPI4.2 status... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for transmitting and receiving SPI4.2 status..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for transmitting and receiving SPI4.2 status... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3973893