Techniques for sequentially transferring data from a memory...

Details Techniques for sequentially transferring data from a memory... Techniques for sequentially transferring data from a memory...

2003-09-26

2008-03-11

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S100000, C711S154000, C711S200000

Reexamination Certificate

active

07343470

ABSTRACT:
Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.

REFERENCES:
patent: 4870302 (1989-09-01), Freeman
patent: 4930107 (1990-05-01), Chan et al.
patent: 5200920 (1993-04-01), Norman et al.
patent: 5237219 (1993-08-01), Cliff
patent: 5543730 (1996-08-01), Cliff et al.
patent: 5581777 (1996-12-01), Kim et al.
patent: 5590305 (1996-12-01), Terrill et al.
patent: 5596734 (1997-01-01), Ferra
patent: 5600819 (1997-02-01), Kamada et al.
patent: 5603001 (1997-02-01), Sukegawa et al.
patent: 5606276 (1997-02-01), McClintock
patent: 5644531 (1997-07-01), Kuo et al.
patent: 5650734 (1997-07-01), Chu et al.
patent: 5680061 (1997-10-01), Veenstra et al.
patent: 5694056 (1997-12-01), Mahoney et al.
patent: 5767734 (1998-06-01), Vest et al.
patent: 5844854 (1998-12-01), Lee
patent: 5869980 (1999-02-01), Chu et al.
patent: 5873113 (1999-02-01), Rezvani
patent: 6011406 (2000-01-01), Veenstra
patent: 6052755 (2000-04-01), Terrill et al.
patent: 6184705 (2001-02-01), Cliff et al.
patent: 6242941 (2001-06-01), Vest et al.
patent: 6314550 (2001-11-01), Wang et al.
patent: 6662291 (2003-12-01), Hashimoto et al.
patent: 6714044 (2004-03-01), Rangan et al.
patent: 2002/0023191 (2002-02-01), Fudeyasu
U.S. Appl. No. 10/106,675, filed Mar. 25, 2002, Rangan et al.
“128Mb, 64Mb, 32Mb Q-Flash Memory, MT28F128J3, MT28F640J3, MT28F320J3,” Micron Technology, Inc. MT28F640J3—7.p65-Rev.6, Aug. 2002, 52 pages total.
“16-megabit 2.7-volt Only Serial DataFlash, AT45DB161,” Atmel, Rev. 0807E-01/01, Jan. 2001, 21 pages total.
“32-megabit 2.7-volt Only DataFlash, AT45DB321B,” Atmel. Rev. 2223E-DFLASH-11/03, Nov. 2003, 32 pages total.
“32-megabit 2.7-volt Only Serial DataFlash, AT45DB321,” Atmel. Rev. 1121E-01/01, Jan. 2001, 21 pages total.
“64-megabit 2.7-volt Only Dual-interface DataFlash, AT45DB642,” Atmel. Rev. 1638F-DFLSH-09/02, Sep. 2002, 37 pages total.
“In-System Programmable Configuration PROM, AT17F040, AT17F080,” Atmel. Rev. 3039D-CNFG-4/03, Apr. 2003, 18 pages total.
“Intel StrataFlash Wireless Memory System (LV18/LV30 SCSP) 768-Mbit LVQ Family with Asynchronous Static RAM Datasheet,” Dec. 2003, 54 pages.
“Using Remote System Configuration with Stratix & Stratix GX Devices,” Altera Corporation. Application Note 217, AN-217-2.1. Nov. 2002, 28 pages total.

Affiliated with

Also associated with

Rating

Techniques for sequentially transferring data from a memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for sequentially transferring data from a memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for sequentially transferring data from a memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3960139