Techniques for segmented CRC design in high speed networks

Details Techniques for segmented CRC design in high speed networks Techniques for segmented CRC design in high speed networks

2007-07-18

2011-10-11

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S758000, C714S821000

Reexamination Certificate

active

08037399

ABSTRACT:
Embodiments of the present invention provide techniques for efficient generation of CRC values in a network environment. Specific embodiments of the present invention enable CRC processing circuits that can generate CRC values at high data throughput rates (e.g., 100 Gbps or greater), while being capable of being implemented on currently available FPGAs. Accordingly, embodiments of the present invention may be used in network devices such as routers, switches, hubs, host network interfaces and the like to support high speed data transmission standards such as 100G Ethernet and beyond.

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