Techniques for reducing off-chip cache memory accesses

Details Techniques for reducing off-chip cache memory accesses Techniques for reducing off-chip cache memory accesses

2008-01-29

2008-01-29

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S159000

Reexamination Certificate

active

07325101

ABSTRACT:
Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cache memory and by designing the replacement algorithm of the on-chip cache memory such that only one line in a given set maps into an off-cache memory cache line, the frequency of off-chip cache memory accesses may be greatly reduced, thereby improving performance and efficiency.

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patent: 5787478 (1998-07-01), Hicks et al.
patent: 5809530 (1998-09-01), Samra et al.
patent: 5909697 (1999-06-01), Hayes et al.
patent: 6321297 (2001-11-01), Shamanna et al.
patent: 6715040 (2004-03-01), Wang et al.
patent: 6748492 (2004-06-01), Rowlands et al.

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