Techniques for providing flexible on-chip termination...

Details Techniques for providing flexible on-chip termination... Techniques for providing flexible on-chip termination...

2006-05-02

2008-09-02

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000

Reexamination Certificate

active

07420386

ABSTRACT:
On-chip termination (OCT) calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5764080 (1998-06-01), Huang et al.
patent: 6064224 (2000-05-01), Esch et al.
patent: 6094069 (2000-07-01), Magane et al.
patent: 6118310 (2000-09-01), Esch et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6384621 (2002-05-01), Gibbs et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6489837 (2002-12-01), Schultz et al.
patent: 6515501 (2003-02-01), Bosnyak et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6605958 (2003-08-01), Bergman et al.
patent: 6798237 (2004-09-01), Wang et al.
patent: 6812732 (2004-11-01), Bui
patent: 6812734 (2004-11-01), Shumarayev et al.
patent: 6836142 (2004-12-01), Lesea et al.
patent: 6836144 (2004-12-01), Bui et al.
patent: 6859064 (2005-02-01), Maangat
patent: 6888369 (2005-05-01), Wang et al.
patent: 6888370 (2005-05-01), Luo et al.
patent: 6894529 (2005-05-01), Chong et al.
patent: 6980022 (2005-12-01), Shumarayev et al.
patent: 7218155 (2007-05-01), Chang et al.
patent: 7221193 (2007-05-01), Wang et al.
patent: 7239171 (2007-07-01), Wang et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 2003/0218477 (2003-11-01), Jang et al.
patent: 2004/0008054 (2004-01-01), Lesea et al.
patent: 2004/0113653 (2004-06-01), Lundberg
patent: 2005/0012533 (2005-01-01), Aoyama et al.
“Virtex-II Pro and Virtex-II Pro X FPGA User Guide,” Mar. 23, 2005, pp. 223-240.
“Stratix II Device Handbook, vol. 2: 4. Selectable I/O Standards in Stretix II & Stretix II GX Devices,” Altera Corporation, Dec. 2005, pp. 4-1 through 4-42.
U.S. Appl. No. 11/356,867, filed Feb. 18, 2006, Santurkar et al.
U.S. Appl. No. 11/364,371, filed Feb. 28, 2006, Shumarayev et al.
U.S. Appl. No. 60/786,129, filed Mar. 27, 2006, Santurkar et al.
U.S. Appl. No. 11/383,937, filed May 17, 2006, Santurkar et al.

Affiliated with

Also associated with

Rating

Techniques for providing flexible on-chip termination... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for providing flexible on-chip termination..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for providing flexible on-chip termination... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3987634