Techniques for providing calibrated parallel on-chip...

Details Techniques for providing calibrated parallel on-chip... Techniques for providing calibrated parallel on-chip...

2006-12-30

2008-10-28

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S087000

Reexamination Certificate

active

07443193

ABSTRACT:
Techniques are provided for calibrating parallel on-chip termination (OCT) impedance circuits. An on-chip termination (OCT) calibration circuit generates first calibration codes and second calibration codes. The first calibration codes control the conductive states of first transistors that are coupled in parallel between a supply voltage and a first terminal. The second calibration codes control the conductive states of second transistors that are coupled in parallel between the first terminal and ground. The OCT calibration circuit selects a first calibration code and a second calibration code and transmits the selected calibration codes to third and fourth transistors to control a parallel on-chip termination impedance at a pin.

REFERENCES:
patent: 5559448 (1996-09-01), Koenig
patent: 5910713 (1999-06-01), Nishi et al.
patent: 5955911 (1999-09-01), Drost et al.
patent: 6064224 (2000-05-01), Esch et al.
patent: 6118310 (2000-09-01), Esch et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6489837 (2002-12-01), Schultz et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6798237 (2004-09-01), Wang et al.
patent: 6812732 (2004-11-01), Bui et al.
patent: 6836144 (2004-12-01), Bui et al.
patent: 7019556 (2006-03-01), Yoo
patent: 7064576 (2006-06-01), Maangat
patent: 7218155 (2007-05-01), Chang et al.
patent: 7221193 (2007-05-01), Wang et al.
patent: 7239171 (2007-07-01), Wang et al.
patent: 7268712 (2007-09-01), Sheen
patent: 2004/0113653 (2004-06-01), Lundberg
patent: 2004/0217774 (2004-11-01), Choe
patent: 2005/0012533 (2005-01-01), Aoyama et al.
patent: 2007/0236247 (2007-10-01), Wang et al.
patent: 2008/0061818 (2008-03-01), Santurkar et al.
U.S. Appl. No. 11/040,343, filed Jan. 20, 2005, Chang et al.
U.S. Appl. No. 11/040,048, filed Jan. 20, 2005, Wang et al.
U.S. Appl. No. 11/381,356, filed May 2, 2006, Wang et al.
U.S. Appl. No. 11/356,867, filed Feb. 18, 2006, Santurkar et al.
U.S. Appl. No. 11/466,451, filed Aug. 22, 2006, Santurkar et al.
U.S. Appl. No. 11/462,702, filed Aug. 5, 2006, Wang et al.

Affiliated with

Also associated with

Rating

Techniques for providing calibrated parallel on-chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for providing calibrated parallel on-chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for providing calibrated parallel on-chip... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4018741