Techniques for providing calibrated on-chip termination...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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C326S086000, C326S108000

Reexamination Certificate

active

11466451

ABSTRACT:
Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5559448 (1996-09-01), Koenig
patent: 5764080 (1998-06-01), Huang et al.
patent: 5955911 (1999-09-01), Drost et al.
patent: 6064224 (2000-05-01), Esch et al.
patent: 6094069 (2000-07-01), Magane et al.
patent: 6118310 (2000-09-01), Esch et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6489837 (2002-12-01), Schultz et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6798237 (2004-09-01), Wang et al.
patent: 6812732 (2004-11-01), Bui et al.
patent: 6812734 (2004-11-01), Shumarayev et al.
patent: 6833729 (2004-12-01), Kim et al.
patent: 6836144 (2004-12-01), Bui et al.
patent: 6876248 (2005-04-01), Nguyen et al.
patent: 6888369 (2005-05-01), Wang et al.
patent: 6888370 (2005-05-01), Luo et al.
patent: 6980022 (2005-12-01), Shumarayev et al.
patent: 7218155 (2007-05-01), Chang et al.
patent: 7221193 (2007-05-01), Wang et al.
patent: 7230448 (2007-06-01), Choe
patent: 7239171 (2007-07-01), Wang et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 2004/0008054 (2004-01-01), Lesea et al.
patent: 2004/0113653 (2004-06-01), Lundberg
patent: 2005/0012533 (2005-01-01), Aoyama et al.
patent: 2007/0236247 (2007-10-01), Wang et al.
U.S. Appl. No. 11/040,343, filed Jan. 20, 2005, Chang et al.
U.S. Appl. No. 11/040,048, filed Jan. 20, 2005, Wang et al.
“Virtex-II Pro and Virtex-II Pro X FPGA User Guide,” Mar. 23, 2005, pp. 223-240.
“Stratix II Device Handbook, vol. 2: 4. Selectable I/O Standards In Stratix II & Stratix II GX Devices,” Altera Corporation, Dec. 2005, pp. 4-1 through 4-42.
“Virtex-4 User Guide,” Mar. 21, 2006.
U.S. Appl. No. 11/462,702, filed Aug. 05, 2006, Wang et al.
U.S. Appl. No. 11/356,867, filed Feb. 18, 2006, Santurkar et al.

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