Techniques for programming and verifying data in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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C714S048000, C714S746000, C714S718000, C360S053000

Reexamination Certificate

active

07058880

ABSTRACT:
The present invention includes techniques for programming and verifying data in a programmable circuit. Programmable circuits such as PLDs may include a plurality of rows and columns of memory cells. Data is programmed into memory elements associated with the rows and columns. Subsequently, the programmed data may be extracted for verification. A first word line may be selected by first word line address bits in row shift registers. Data programmed into the first word line is loaded into column shift registers for verification during one or more verify steps. During a program step, data is programmed into memory elements in a second word line that is selected by the first word line address bits. The present invention also provides a technique for shifting program data bits into the column shift registers at the same time that verify data bits are shifted out of the column shift registers.

REFERENCES:
patent: 5479370 (1995-12-01), Furuyama et al.
patent: 5598108 (1997-01-01), Pedersen
patent: 5668772 (1997-09-01), Hotta
patent: 5970005 (1999-10-01), Yin et al.
patent: 5996091 (1999-11-01), Jones et al.
Altera Corporation “MAX 7000 Programmable Logic Device Family” May 1999.
Prepared by the In-System Configuration Working Group of the Test Technology Technical Council of the IEEE Computer Society, “Draft Standard for In-System Configuration of Programmable Devices”, IEEE, Unapproved Draft May 5, 2000.

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