Techniques for placing dummy features in an integrated...

Details Techniques for placing dummy features in an integrated... Techniques for placing dummy features in an integrated...

2007-03-27

2007-03-27

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11016077

ABSTRACT:
In one embodiment, a dummy pattern having a plurality of dummy features (e.g., waffles) are employed to help achieve a relatively planar surface by chemical-mechanical planarization (CMP). The dummy features are placed based on a dielectric pattern density of a region of an integrated circuit. The dummy features may be added to the design of the integrated circuit using a one pass or two pass approach. The dummy features in a second pass may be fragmented using an AndNot algorithm, for example.

REFERENCES:
patent: 6346717 (2002-02-01), Kawata
patent: 6747321 (2004-06-01), Kanamori
patent: 6748579 (2004-06-01), Dillon et al.
patent: 6782512 (2004-08-01), Asakawa

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