Techniques for optimizing design of a hard intellectual...

Details Techniques for optimizing design of a hard intellectual... Techniques for optimizing design of a hard intellectual...

2008-08-18

2010-11-30

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S016000, C326S041000, C326S046000

Reexamination Certificate

active

07843216

ABSTRACT:
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

REFERENCES:
patent: 6879598 (2005-04-01), Zancan et al.
patent: 6894530 (2005-05-01), Davidson et al.

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