Techniques for operating non-volatile memory systems with...

Details Techniques for operating non-volatile memory systems with... Techniques for operating non-volatile memory systems with...

2000-11-22

2004-01-27

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S171000, C711S172000

Reexamination Certificate

active

06684289

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to semiconductor memory systems, particularly to non-volatile memory systems, and has application to flash electrically-erasable and programmable read-only memories (EEPROMs).
Flash EEPROM systems are being applied to a number of applications, particularly when packaged in an enclosed card that is removably connected with a host system. Current commercial memory card formats include that of the Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF), MultiMediaCard (MMC) and Secure Digital (SD). One supplier of these cards is SanDisk Corporation, assignee of this application. Host systems with which such cards are used include personal computers, notebook computers, hand held computing devices, cameras, audio reproducing devices, and the like. Flash EEPROM systems are also utilized as bulk mass storage embedded in host systems.
Such non-volatile memory systems include an array of floating-gate memory cells and a system controller. The controller manages communication with the host system and operation of the memory cell array to store and retrieve user data. The memory cells are grouped together into blocks of cells, a block of cells being the smallest grouping of cells that are simultaneously erasable. Prior to writing data into one or more blocks of cells, those blocks of cells are erased. User data are typically transferred between the host and memory array in sectors. A sector of user data can be any amount that is convenient to handle, preferably less than the capacity of the memory block, often being equal to the standard disk drive sector size, 521 bytes. In one commercial architecture, the memory system block is sized to store one sector of user data plus overhead data, the overhead data including information such as an error correction code (ECC) for the user data stored in the block, a history of use of the block, defects and other physical information of the memory cell block. Various implementations of this type of non-volatile memory system are described in the following United States patents and pending applications assigned to SanDisk Corporation, each of which is incorporated herein in its entirety by this reference: U.S. Pat. Nos. 5,172,338, 5,602,987, 5,315,541, 5,200,959, 5,270,979, 5,428,621, 5,663,901, 5,532,962, 5,430,859 and 5,712,180, and application Ser. No. 08/910,947, filed Aug. 7, 1997, now U.S. Pat. No. 6,222,762, and Ser. No. 09/343,328, filed Jun. 30, 1999, now U.S. Pat. No. 6,151,248.
Another type of non-volatile memory system utilizes a larger size memory cell block that each stores multiple pages per block, a page being a minimum unit of data that is programmed as part of a single programming operation. One sector of user data, along with overhead data related to the user data and the block in which such data is being stored, are typically included in a page. Yet another specific system that has been commercially available from SanDisk Corporation for more than one year from the filing date hereof, stores overhead data related to the user data being stored, such as ECC, along with the user data in a common sector, while overhead data related to the block in which the sector is stored is written as part of a different sector in a different block. An example of this system is given in patent application Ser. No. 09/505,555, filed Feb. 17, 2000, U.S. Pat. No. 6,426,893, which patent is incorporated herein in its entirety by this reference.
One architecture of the memory cell array conveniently forms a block from one or two rows of memory cells that are within a sub-array or other unit of cells and which share a common erase gate. U.S. Pat. Nos. 5,677,872 and 5,712,179 of SanDisk Corporation, which are incorporated herein in their entirety, give examples of this architecture. Although it is currently most common to store one bit of data in each floating gate cell by defining only two programmed threshold levels, the trend is to store more than one bit of data in each cell by establishing more than two floating-gate transistor threshold ranges. A memory system that stores two bits of data per floating gate (four threshold level ranges or states) is currently available, with three bits per cell (eight threshold level ranges or states) and four bits per cell (sixteen threshold level ranges) being contemplated for future systems. Of course, the number of memory cells required to store a sector of data goes down as the number of bits stored in each cell goes up. This trend, combined with a scaling of the array resulting from improvements in cell structure and general semiconductor processing, makes it practical to form a memory cell block in a segmented portion of a row of cells. The block structure can also be formed to enable selection of operation of each of the memory cells in two states (one data bit per cell) or in some multiple such as four states (two data bits per cell), as described in SanDisk Corporation U.S. Pat. No. 5,930,167, which is incorporated herein in its entirety by this reference.
Since the programming of data into floating-gate memory cells can take significant amounts of time, a large number of memory cells in a row are typically programmed at the same time. But increases in this parallelism cause increased power requirements and potential disturbances of charges of adjacent cells or interaction between them. U.S Pat. No. 5,890,192 of SanDisk Corporation, which is incorporated herein in its entirety, describes a system that minimizes these effects by simultaneously programming multiple chunks of data into different blocks of cells located in different operational memory cell units (sub-arrays).
The foregoing referenced patents describe a memory array design wherein the individual memory cells are connected between adjacent bit lines in rows that include word lines, a “NOR” architecture. A “NAND” architecture is also commercially popular for non-volatile memory arrays, wherein a string of many memory cells are connected together in series between individual bit lines and a reference potential, rows of cells being formed from one cell of each of many such strings. Other specific architectures are also suggested in the literature. The foregoing referenced patents also describe the use of a type of non-volatile memory cell utilizing one or two floating gates made of a conductive material on which a level of electron charge is stored to control the effective threshold level of the cell. Alternative technologies for storing electrons, useful in various memory array architectures, includes those that trap electrons in a dielectric layer between two dielectric layers, rather than using conductive floating gates. Additionally, the foregoing referenced patents further describe the use of erase gates to which charge is removed from the cells' storage elements during an erasure of one or more blocks at a time. An alternative technique erases electrons from the storage element to the substrate as an erase electrode.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, briefly and generally, rather than constraining one or some integer number of sectors of user data and accompanying overhead data to fill the individual data pages, at least some such sectors of data are split between two or more pages of memory. In one configuration, one or more sectors of user data, along with all the accompanying overhead data, a portion of the overhead data or none of the overhead data, are programmed together in one page of the memory while other sectors similarly constituted are divided and programmed into two or more pages in a manner that effectively utilizes the storage capacity of the pages. In a another configuration, the individual sectors of user data, with or without at least some part of its overhead data, are larger than the capacity of the pages in which they are stored, resulting in virtually every such sector being split between two pages. These approaches open up many possibilities for efficient use of a particular memory block and page

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