Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-09-10
2004-11-30
Elmore, Stephen (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S104000, C711S105000, C711S152000, C711S163000, C711S170000, C711S172000, C711S173000, C365S189011, C365S189020, C365S230010, C365S230020, C365S230030, C365S230040, C365S230050
Reexamination Certificate
active
06826657
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory systems and, more particularly, to techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules.
BACKGROUND OF THE INVENTION
Most electronic memory systems permit two or more memory modules to be connected to each memory port of a memory controller. This feature allows a memory system manufacturer to connect one memory module to each memory controller port, while still allowing a memory system owner to later upgrade the memory system by adding at least one additional memory module to each memory controller port.
However, in memory systems having a high rate of data signaling or other restrictive signaling requirements, only a single memory module is permitted to be connected to each memory controller port. This is sometimes called a point-to-point connection topology, or a port-per-module memory system. When a memory system is constrained in this fashion, and when it is still necessary to allow the memory system to be upgraded at least once after its initial manufacture, then problems can arise when the memory capacities of the initial memory module and the additional memory module(s) do not match.
To illustrate these problems, it is useful to first describe memory systems having point-to-point memory module connections wherein only a single memory module is employed or multiple memory modules of matching memory capacity are employed. For example,
FIG. 1
illustrates two such memory systems having point-to-point memory module connections. More particularly,
FIG. 1A
shows a memory system
10
with one memory module
12
connected to a first port
14
of a memory controller
16
.
FIG. 1B
shows a memory system
20
with the first memory module
12
connected to the first port
14
of the memory controller
16
, and a second memory module
28
connected to a second port
30
of the memory controller
16
.
The memory modules
12
and
28
in
FIGS. 1A and 1B
are divided into ranks (rows) of memory components (MEM)
32
. The number of ranks is denoted NR, and may vary from module to module. Note that in some memory systems the point-to-point connection constraint may extend to the memory component as well as the memory module. In such a case, the number of ranks NR is limited to one.
The memory modules
12
and
28
in
FIGS. 1A and 1B
are also divided into slices (columns) of memory components (MEM)
32
. The number of slices is denoted N
s
, and may also vary from module to module. However, the number of slices N
s
times the number of data-type signals per slice N
dq
is a constant (N
DQ
=N
s
*N
dq
) determined by the number of data-type signals at a memory controller port N
DQ
.
The notion of “slice” is used to distinguish address-type signals “A” from data-type signals “QD”. The data-type signals (QD) from a slice of a memory controller port are only connected to a corresponding slice of each rank of memory components in a memory module. The address-type signals (A) are connected to all slices of each rank of memory components in a memory module. The address-type signals (A) can usually fan-out to more memory components than can data-type signals for several reasons including: [1] the signaling rate of address-type signals (A) is typically lower than data-type signals, and [2] address-type signals (A) are typically unidirectional (flowing from memory controller to memory components) and data-type signals (QD) are typically bi-directional (flowing in one direction at one time and flowing in the opposite direction at another time).
In addition to memory components (MEM)
32
, each memory module
12
and
28
also contains some form of termination structure (T)
22
at the end of each signal wire. This is typically some sort of resistor component, and is typically required due to high signaling rates in a memory system.
Other connection topologies within a memory module are also possible, and will be described in detail below. The topologies shown in
FIG. 1
are representative of these other connection topologies, and are used as an example to illustrate the problem arising from the need to upgrade memory systems with point-to-point connections between memory controller and memory module(s).
FIG. 2
shows the internal detail of the memory component (MEM)
32
that is used in the memory modules of FIG.
1
. The address-type signals (A) typically comprise row signals (A
RCLK
/A
RSTROBE
, A
REN
, OP
R
, A
BR
, and A
R
) and column signals (A
RCLK
/A
CSTROBE
, A
CEN
, OP
C
, A
BC
, and A
C
). The data-type signals (QD) typically comprise read signals (Q
EN
, Q
CLK
, Q
STROBE
, and Q) and write signals (D
EN
, D
CLK
, D
STROBE
, D and DM). Both the address-type signals (A) and the data-type signals (QD) are used to control access to 2
NB
banks of memory core
34
.
A
RCLK
/A
RSTROBE
is a timing signal which is used to indicate when other row signals carry valid information. Such a timing signal is usually called a “clock” or “strobe” signal. A
REN
is a control signal which is optionally present. It is an “enable” signal that can indicate when the valid information carried by other row signals is to be used or ignored by the memory component (MEM)
32
. OP
R
is a set of signals (a set of Nopr wires) that is used to indicate what type of row operation is to take place. A
BR
is a set of signals (a set of Nb wires) that is used to indicate the bank address for a row operation. A
R
is a set of signals (a set of Nr wires) that is used to indicate the row address for a row operation. Three row decode blocks
36
are provided which include storage elements (registers and/or latches) and logic that are needed to provide row control signals to the memory core
34
at the appropriate time.
A
CCLK
/A
CSTROBE
is timing signal which is used to indicate when other column signals carry valid information. Such a timing signal is usually called a “clock” or “strobe” signal. A
CEN
is a control signal which is optionally present. It is an “enable” signal that can indicate when the valid information carried by other column signals is to be used or ignored by the memory component. OP
c
is a set of signals (a set of Nopc wires) that is used to indicate what type of column operation is to take place. A
BC
is a set of signals (a set of Nb wires) that is used to indicate the bank address for a column operation. A
C
is a set of signals (a set of Nc wires) that is used to indicate the column address for a column operation. Three column decode blocks
38
are provided which include storage elements (registers and/or latches) and logic that are needed to provide column control signals to the memory core
34
at the appropriate time.
Note that in some memory components, some of the above sets of signals could share the same wires. However, these signals are shown in
FIG. 2
in unshared form for purposes of descriptive clarity.
There are two principle types of row operation: activate and precharge. When an activate operation is indicated, one of the 2
Nr
rows of the 2
nB
banks of the memory core
34
is selected by row drivers
40
of the memory core
34
. (2
NC
*M*N
dq
) bits of the selected row are then sensed and latched by column sense amplifiers
42
of the memory core
34
. When a precharge operation is indicated, the column sense amplifiers
42
, row drivers
40
, and other circuitry of the memory core
34
are returned to a precharged state to await the next activate operation.
There are two principle types of column operation: read and write. When a read operation is indicated, one of the 2
Nc
columns of the 2
Nb
banks of the memory core
34
is selected, and (M*N
dq
) bits of the selected column are transferred to a multiplexer
44
. This data is grouped into “M” sets of “N
dq
” bits. The multiplexer
44
, which performs a parallel-to-serial conversion on the data, transfers “N
dq
” bits at a time (repeated “M” separate times) to “N
dq
” data output pins (Q). Q
CLK
and Q
STROBE
are timing signals which are asserted and generated, respectively
Hampel Craig E.
Perego Richard E.
Tsern Ely K.
Ware Frederick A.
Elmore Stephen
Hunton & Williams LLP
Rambus Inc.
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