Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-04-26
2011-04-26
Richards, N Drew (Department: 2895)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C703S015000, C438S001000, C365S072000
Reexamination Certificate
active
07932563
ABSTRACT:
An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer overlying the transistor array produces stress in a channel region of the transistor.
REFERENCES:
patent: 6461905 (2002-10-01), Wang et al.
patent: 6875680 (2005-04-01), Park
patent: 7049185 (2006-05-01), Ito
patent: 7423283 (2008-09-01), Luo et al.
patent: 2006/0220066 (2006-10-01), Yoshida
patent: 2007/0228279 (2007-10-01), Matsumoto et al.
patent: 2007/0246776 (2007-10-01), Moroz et al.
patent: 2007/0267707 (2007-11-01), Tsutsui
patent: 2008/0003789 (2008-01-01), Chen et al.
patent: 2008/0014690 (2008-01-01), Chu et al.
patent: 2008/0057653 (2008-03-01), Chidambarrao et al.
patent: 2008/0296699 (2008-12-01), Hong et al.
patent: 2009/0023261 (2009-01-01), Hirano
patent: 2009/0189199 (2009-07-01), Moriyama et al.
patent: 2009/0190387 (2009-07-01), Kim
patent: 2010/0019325 (2010-01-01), Nakamura et al.
patent: 1 858 067 (2007-11-01), None
patent: WO 2008/025661 (2008-03-01), None
patent: WO 2008/108339 (2008-09-01), None
Moroz et al, “analyzing strained-silicon options for stress-engineering transistors”, Solid State Technology, Jul. 2004.
Aikawa H. et al., “Variability Aware Modeling and Characterization in Standard Cell in 45 nm CMOS with Stress Enhancement technique,”2008 Symposium on VLSI Technology, Digest of Technical Papers, Jun. 17, 2008, pp. 90-91, IEEE, Piscataway, New Jersey, USA.
Ho Jung-Ching J.
Sowards Jane W.
Wu Shuxian
Bradford Peter
Cartier Lois D.
Hewett Scott
Maunu LeRoy D.
Richards N Drew
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