Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2007-05-15
2007-05-15
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S037000, C326S038000, C326S039000, C326S040000, C326S041000, C326S047000
Reexamination Certificate
active
11007827
ABSTRACT:
Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.
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Ang Boon Jin
Ng Bee Yee
Altera Corporation
Barnie Rexford
Townsend and Townsend / and Crew LLP
White Dylan
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