Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-18
2005-10-18
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06957412
ABSTRACT:
Techniques are provided that combine functional blocks in a user design into fewer programmable circuit elements. Systems and methods of the present invention can combine functional blocks in a user design into a single programmable circuit element. A plurality of functional blocks in a user design that can be combined are identified. The possible combinations of functional blocks can be sorted according to a gain function. The gain function can, for example, weigh routing delays caused by a combination. The most desirable combination is selected from the sorted list of possible combinations. The selected combination is checked to see if it is feasible in light of electrical and user-specified constraints. If the combination is feasible, the combination is performed. Combinations continue to be performed by selecting the most desirable combinations from the sorted list.
REFERENCES:
patent: 6727726 (2004-04-01), Plants
patent: 6829756 (2004-12-01), Trimberger
Wen-Jong Fang et al., Multiway FPGA Partitioning by Fully Exploiting Design Hierarchy, ACM Transactions of Design Automation of Electronic Systems, pp. 34-50, Jan. 2000.
E. Bozorgzadeh et al., RPACK: Routability-Driven Packing for Cluster-based FPGAs, Proceedings of the 2001 Conference on Asia South Pacific Design Automation, pp. 629-634, Jan. 2001.
Wen-Jong Fang et al., Performance-Drive Multi-FPGA Partitioning Using Functional Clustering and Replication, Proceedings of the 35th Annual Conference on Design Automation. pp. 283-386, May 1998.
A. Marquardt et al., Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density, Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, pp. 37-46, Feb. 1999.
Betz, V. et al. (1999).Architecture and CAD for Deep-Submicron FPGAs,Chapters 1-3, Kluwer Academic Publishers,Norwell, Massachusetts, 63 pages total.
Fang et al., “Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication”, DAC 98.
Marquardt et al., “Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density”, FPGA 99.
Fang et al., “Multiway FPGA Partitioning by Fully Exploiting Design Hierarchy”, ACM Transactions on Design Automation of Electronic Systems, vol. 5, No. 1, Jan. 2000.
Bozorgzadeh et al., “RPack: Routability-Driven packing for cluster-based FPGAs”, IEEE 2001.
Ahmed Elias
Betz Vaughn
Neto David
Altera Corporation
Thompson A. M.
Townsend and Townsend / and Crew LLP
LandOfFree
Techniques for identifying functional blocks in a design... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for identifying functional blocks in a design..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for identifying functional blocks in a design... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3456468