Techniques for grouping circuit elements into logic blocks

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10716309

ABSTRACT:
Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.

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“Using the Quartus II Chip Editor,” Application Note 310, version 1.0, Altera Corporation San Jose, CA (Jun. 2003).

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