Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-09-18
2010-10-26
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S755000, C714S786000
Reexamination Certificate
active
07823041
ABSTRACT:
Techniques are described herein that can be used to decode signals received over multiple channels. The received signals may be processed using noise reducing logic. Signal-to-noise ratio information per channel for signals received over each of the multiple channels may be considered to determine reliability information concerning the slicer input for each channel. Low density parity check codes or other forward error correction (FEC) codes may be used to decode the processed signals from all the multiple channels based on the reliability information.
REFERENCES:
patent: 2004/0057535 (2004-03-01), Strolle et al.
patent: 2006/0107179 (2006-05-01), Shen et al.
Gallager, R.G., “Low-Density Parity-Check Codes”, IRE Transactions on Information Theory, vol. 8, Jan. 1962, pp. 21-28.
Mackay, David J.C. et al., “Near Shannon Limit Performance of Low Density Parity Check Codes”, Electronics Letters, Mar. 13, 1997, vol. 33, No. 6, pp. 1-4.
Ungerboeck, Gottfried, “10GBASE-T Coding and Modulation: 128-DSQ + LDPC”, IEEE P802.3an Sep./Oct. 2004 interim meeting (Sep. 2004).
Birenboim Harry
Mezer Amir
Choi Glen B
Intel Corporation
Lamarre Guy J
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