Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2007-07-10
2007-07-10
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S037000, C326S038000, C326S039000, C326S040000, C326S047000, C716S030000, C710S100000, C710S104000, C710S120000
Reexamination Certificate
active
11003586
ABSTRACT:
Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.
REFERENCES:
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 6091262 (2000-07-01), New
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6102963 (2000-08-01), Agrawal
patent: 6145020 (2000-11-01), Barnett
patent: 6212639 (2001-04-01), Erickson et al.
patent: 6242945 (2001-06-01), New
patent: 6259271 (2001-07-01), Couts-Martin et al.
patent: 6260087 (2001-07-01), Chang
patent: 6337579 (2002-01-01), Mochida
patent: 6441641 (2002-08-01), Pang et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6526563 (2003-02-01), Baxter
patent: 6538468 (2003-03-01), Moore
patent: 6737884 (2004-05-01), Shigemasa et al.
patent: 6766406 (2004-07-01), Gasperini et al.
patent: 6842034 (2005-01-01), Chan et al.
patent: 6918027 (2005-07-01), Mantey et al.
patent: 7034569 (2006-04-01), Balasubramanian et al.
patent: 2004/0061147 (2004-04-01), Fujita et al.
patent: 2005/0093572 (2005-05-01), Sun et al.
patent: 2005/0102573 (2005-05-01), Sun et al.
patent: 2005/0237083 (2005-10-01), Bakker et al.
U.S. Appl. No. 10/654,518, filed Sep. 2, 2003, Tyson.
“Atlantic Interface,” Altera Functional Specification 13, version 3.0, Altera Corporation San Jose, CA (Jun. 2002).
“FPGAs & FPSCs from Lattice: ORSPI4,” product information from http://www.latticesemi.com, Lattice Semiconductor Corporation Hillsboro, OR (2003), no month.
“ORCA® ORSPI4 Dual SPI4 Interface and High Speed Serdes FPSC,” product information Lattice Semiconductor Corporation Hillsboro, OR (2004), no month.
System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices, Optical Internetworking Forum Implementation Agreement : OIF-SPI4-02.0 (Jan. 2001).
Betz et al.Architecture and CAD for Deep-Submicron FPGAs, 2nd printingKluwer Academic Publishers, chapters 2, 4, 5, and 7 (1999), no month.
Ang Boon Jin
Camarota Rafael
Chong Thow Pang
Rahim Irfan
Altera Corporation
Barnie Rexford
White Dylan
LandOfFree
Techniques for combining volatile and non-volatile... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for combining volatile and non-volatile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for combining volatile and non-volatile... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3816894