Techniques for calibrating on-chip termination impedances

Details Techniques for calibrating on-chip termination impedances Techniques for calibrating on-chip termination impedances

2008-05-13

2008-05-13

Le, Don (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S027000, C326S083000

Reexamination Certificate

active

07372295

ABSTRACT:
A calibration circuit block includes a first resistor network, a second resistor network, and a feedback loop. The first resistor network includes a set of transistors and receives a constant current from a constant current source. The second resistor network receives a tracking current from a tracking current source. The impedance of the second resistor network changes with temperature and process variations on the integrated circuit. The tracking current source compensates for variations in the impedance of the second resistor network that are caused by process and temperature variations to maintain a constant reference voltage at the second resistor network. The feedback loop generates calibration control signals for controlling the conductive states of the transistors in the first resistor network. The feedback loop adjusts the calibration control signals to maintain a constant impedance in the first resistor network.

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