Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2000-08-10
2003-12-30
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S036000, C713S400000, C713S600000
Reexamination Certificate
active
06671754
ABSTRACT:
This invention was made with Government support under a Government contract. The Government has certain rights in this invention.
TECHNICAL FIELD OF THE INVENTION
This invention relates to information processors that receive input data from a multiplicity of sources, and more particularly to techniques for alignment of the data.
BACKGROUND OF THE INVENTION
The invention applies to any processing system where multiple asynchronous data sources are used in a coordinated manner. Such processing systems include multiple, parallel processors sharing computational load, multiple processors operating redundantly for fault tolerance via real time comparison or voting, and systems requiring high bandwidth data distribution using multiple links to share data.
SUMMARY OF THE INVENTION
Techniques are described for converting input data from a multiplicity of sources that are mutually asynchronous, to a single, common synchronous format for local processing by an information processor. In accordance with an aspect of the invention, a set of logical operations is described which control first-in-first-out (“FIFO”) buffers to align all inputs to a predetermined point in the data flow or processing sequence, and which maintain clock-by-clock alignment of the input data sequences for an indefinite period of time thereafter.
Thus, in accordance with an aspect of the invention, a method is described for converting input data from a multiplicity of data sources that are mutually asynchronous, to a single, common synchronous format. The method comprises:
receiving each asynchronous data input from each of the data sources in a respective first-in, first-out buffer (FIFO) device;
controlling the readout of data from the respective FIFO devices to provide a microtiming function to assure that sequential samples of data from the asynchronous data sources step together, one at a time out of their respective FIFOs without loss of registration, and to provide a macrotiming function to initially align a predetermined start point of a sequence of data among all of the data sources.
In accordance with another aspect of the invention, a system is described for converting input data sequences from a multiplicity of data sources that are mutually asynchronous, to a single, common synchronous format. The system includes a set of first-in-first-out (FIFO) buffer devices, connected to receive the data input sequences from the data sources. A control logic system controls readout of data from the FIFO buffer devices, and includes macrotiming circuitry for aligning all data inputs to a predetermined point in data flow or processing sequence, and microtiming circuitry for maintaining clock-by-clock alignment of the input data sequences.
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Alkov Leonard A.
Gaffin Jeffrey
Lenzen, Jr. Glenn H.
Mai Rijue
Raytheon Company
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