Techniques and circuits for high yield improvements in programma

Details Techniques and circuits for high yield improvements in programma Techniques and circuits for high yield improvements in programma

1996-06-12

2000-11-14

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712 11, 712 39, 713310, 365201, 36523006, G06F 126

Patent

active

061483907

ABSTRACT:
A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

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MacArthur, James B., Lacey, Timothy M.: U.S. Patent Application entitled "Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Routing Resources," filed Jun. 12, 1996; Application No.: 08/662,056.
MacArthur, James B., Lacey, Timothy M.: U.S. Patent Application entitled "Techniques and Circuits for High Yield Improvements in Programmmable Devices Using Redundant Routing Resources," mailed Jun. 12, 1996, Express Mail No. TB907643737US.

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