Electrical computers and digital processing systems: support – Computer power control – By external command
Reexamination Certificate
2000-04-24
2002-02-12
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: support
Computer power control
By external command
C713S322000, C713S323000, C714S006130, C714S011000, C714S014000, C714S022000, C712S040000
Reexamination Certificate
active
06347378
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits. More particularly, the present invention relates to the field of programmable logic devices.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs), sometimes referred to as PALs, PLAs, FPLAs, PLDs, FPLDs, EEPLDs, LCAs and FPGAs, allow the user to electrically program standard, off-the-shelf integrated circuit logic devices to meet the specific needs of his/her particular application. Thus, proprietary and standard logic functions can be designed and fabricated in-house by using programmable logic devices without the long engineering lead times, the high tooling costs, and the complex procurement and inventory issues associated with application specific integrated circuits (ASIC) devices.
Such programmable logic devices include a plurality of logic blocks that may be user configurable and are interconnected via a programmable interconnect structure. The plurality of logic blocks, often referred to as macrocells, are typically arranged in an array or matrix structure. By interconnecting the logic blocks via the interconnect structure, the programmable logic device can be programmed to perform complex logic functions.
Interconnect structures having a plurality of horizontal and vertical routing lines are typically arranged in a grid-like structure. The routing lines are metal lines or wires (or other conductive materials) that carry signals to and from the used logic blocks. Located at every or almost every interconnect point of a horizontal routing line and a vertical routing line is a programmable element that creates a cross-link when programmed and located at every or almost every interconnect point of two horizontal routing lines or two vertical routing lines is a programmable element that creates a pass-link when programmed. The cross-link is used to either couple or decouple the horizontal and vertical routing lines at an interconnect point while the pass-link is used to either couple or decouple two segments of a routing line. The programmable elements may be fuses or antifuses which can be programmed to respectively connect or disconnect the routing lines at the interconnect point. It is appreciated that other types of programmable elements may be used as well such as Static Random Access Memories (SRAMs) and flash Electrically Erasable Programmable Read-Only Memories (EEPROMs). It is also appreciated that the various programmable elements may be used in various parts of a PLD such as the macrocells, product term matrix, and the “OR” term array.
A fuse is a device having two electrodes and a conductive element which electrically connects the two electrodes. When a fuse (of one embodiment) is programmed, by passage of sufficient current between its electrodes, the two electrodes are electrically disconnected. Laser fuses are programmed by using a laser to disconnect the electrodes. By contrast, an antifuse is a device having two electrodes which are not electrically connected when unprogrammed. However, when programmed, the first and second electrodes of the antifuse are permanently electrically connected. An antifuse (of one embodiment) is programmed by applying sufficient voltage (“programming voltage”) between its first and second electrodes, thereby forming a bi-directional conductive link between the first and the second electrodes.
In order to program a programmable logic device, the user inputs a logic circuit design into a computer using one of a variety of design entry options. Possible design entry options include hierarchical schematic capture, a hardware description language, Boolean equations, state machine diagrams, truth table, netlist, and microcoded assembly language. After the logic circuit design is entered into the computer, the computer maps the logic circuit design into the programmable logic device in order to implement the logic circuit design when programmed. During programming, a path is routed through the interconnect structure by selectively programming the programmable elements at each interconnect point of the routing lines in the path. In other words, the used logic blocks are coupled to the interconnect structure by programming programmable elements such that the appropriate voltage signals can be applied to the input/output ports of each selected logic block.
During the manufacturing and testing of a programmable logic device, the device may be found to have defective logic. If the programmable element is a one-time programmable device such as a fuse or antifuse, a routing failure due to a bad logic block may cause the entire programmable logic device to be defective. This type of failure often requires the user to dispose of the device. However, if alternative logic blocks that can be utilized by the programming software are available to correct such a defect, the programmable logic device is functional despite such failures. In the past, unused redundant routing resources and/or logic blocks were available in some programmable logic devices but there was no way for the programming software to utilize these redundant elements. Therefore, to reduce the probability of producing defective programmable logic devices, it is desirable to provide a programmable logic device having redundant logic blocks that can be utilized by the programming software.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention describes a programmable logic device having redundant logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of logic blocks, a plurality of routing resources and a programming circuit. At least one routing resource corresponds to a logic block. When a logic block is enabled, its corresponding routing resource is capable of being configured to provide input and output data paths to the enabled logic block and when a logic block is disabled, its corresponding routing resource is capable of being configured to bypass the disabled logic block. The programming circuit is capable of storing configuration data and is capable of providing the configuration data to the routing resources that correspond to an enabled set of logic blocks.
The present invention also concerns a method for programming a programmable logic device having redundant sets of logic blocks. At least one of the functional sets of logic blocks is enabled for programming and at least one of the nonfunctional sets of logic blocks is disabled from programming. Each routing resource that corresponds to a functional set of logic blocks is configured to provide its corresponding functional set of logic blocks with input and output data paths.
It is desirable in certain embodiments to provide a programmable logic device that has the software capability to program around a bad or nonfunctional logic block or row/column of logic blocks. By making the bad logic blocks appear transparent, only the functional logic blocks are visible to the programming software. Therefore, programming is simplified by having the software program only the functional logic blocks without attempting to program the nonfunctional logic blocks and not taking the nonfunctional logic blocks into account when programming the functional logic blocks.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Lacey Timothy
MacArthur James
Pan Daniel H.
Quicklogic Corp.
Wagner , Murabito & Hao LLP
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