Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-28
2001-05-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S110000, C702S185000
Reexamination Certificate
active
06237131
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits. More particularly, the present invention relates to the field of programmable logic devices.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs), sometimes referred to as PALs, PLAs, FPLAS, PLDs, FPLDs, EEPLDs, LCAs and FPGAs, allow the user to electrically program standard, off-the-shelf integrated circuit logic devices to meet the specific needs of their particular application. Thus, proprietary and standard logic functions can be designed and fabricated in-house by using programmable logic devices without the long engineering lead times, the high tooling costs, and the complex procurement and inventory issues associated with application specific integrated circuits (ASIC) devices.
Such programmable logic devices include a plurality of user-configurable logic blocks that are interconnected via an interconnect structure. The plurality of user-configurable logic blocks, often referred to as macrocells, are typically arranged in an array or matrix structure. By interconnecting the user-configurable logic blocks via the interconnect structure, the programmable logic device can be programmed to perform complex logic functions.
Interconnect structures having a plurality of horizontal and vertical routing lines are typically arranged in a grid-like structure. The routing lines are metal lines or wires (or other conductive materials) that carry signals to and from the used logic blocks. Located at every or almost every interconnect point of a horizontal routing line and a vertical routing line is a programmable element that creates a cross-link when programmed and located at every or almost every interconnect point of two horizontal routing lines or two vertical routing lines is a programmable element that creates a pass-link when programmed. The cross-link is used to either couple or decouple the horizontal and vertical routing lines at an interconnect point while the pass-link is used to either couple or decouple two segments of a routing line. The programmable elements may be fuses or antifuses which can be programmed to respectively connect or disconnect the routing lines at the interconnect point. It is appreciated that other types of programmable elements may be used as well such as Static Random Access Memories (SRAMs) and flash Electrically Erasable Programmable Read-Only Memories (EEPROMs). It is also appreciated that the various programmable elements may be used in various parts of a PLD such as the macrocells, product term matrix, and the “OR” term array.
A fuse is a device having two electrodes and a conductive element which electrically connects the two electrodes. When a fuse (of one embodiment) is programmed, by passage of sufficient current between its electrodes, the two electrodes are electrically disconnected. Laser fuses are programmed by using a laser to disconnect the electrodes. By contrast, an antifuse is a device having two electrodes which are not electrically connected when unprogrammed. However, when programmed, the first and second electrodes of the antifuse are permanently electrically connected. An antifuse (of one embodiment) is programmed by applying sufficient voltage (“programming voltage”) between its first and second electrodes, thereby forming a bi-directional conductive link between the first and the second electrodes.
In order to program a programmable logic device, the user inputs a logic circuit design into a computer using one of a variety of design entry options. Possible design entry options include hierarchical schematic capture, a hardware description language, Boolean equations, state machine diagrams, truth table, netlist, and microcoded assembly language. After the logic circuit design is entered into the computer, the computer maps the logic circuit design into the programmable logic device in order to implement the logic circuit design when programmed. During programming, a path is routed through the interconnect structure by selectively programming the programmable elements at each interconnect point of two routing lines or two segments of a routing line in the path. In other words, the logic blocks selected for programming are coupled to the interconnect structure during routing such that the appropriate voltage signals can be applied to the input/output ports of each selected logic block.
During the manufacturing and testing of a programmable logic device, the device may be found to have a defective programmable element. If the programmable element is a one-time programmable device such as a fuse or antifuse, a routing failure due to the failure of a programmable element in the routing path may cause the entire programmable logic device to be defective. This type of failure often requires the user to dispose of the device. However, if alternative routing resources are available to correct such a defect, the programmable logic device is functional despite such failures. Therefore, to reduce the probability of producing defective programmable logic devices, it is desirable to provide a programmable logic device having redundant routing resources.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device having a plurality of routing lines that are selectively coupled to at least one logic block in the programmable logic device. Located at the interconnect point of at least two routing lines or two segments of a routing line is a programmable element. The programmable element includes at least two interconnect circuits coupled in parallel.
The present invention also concerns a method for programming an integrated circuit. A path though a plurality of routing lines is selected in order to configure the selected logic blocks. The path is routed by programming the programmable elements located at the interconnect points along the path. At least one of the programmable elements selected for programming includes a plurality of interconnect circuits coupled in parallel. During the programming of the integrated circuit, the nonfunctional programmable elements in the path are detected such that the path is rerouted to bypass the nonfunctional programmable element.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 4920497 (1990-04-01), Updadhyaya et al.
patent: 4974048 (1990-11-01), Chakravorty et al.
patent: 5011791 (1991-04-01), Mastroianni
patent: 5087958 (1992-02-01), Chen et al.
patent: 5200652 (1993-04-01), Lee
patent: 5293133 (1994-03-01), Birkner et al.
patent: 5349248 (1994-09-01), Parlour et al.
patent: 5371422 (1994-12-01), Patel et al.
patent: 5414364 (1995-05-01), McCollum
patent: 5491664 (1996-02-01), Phelan
patent: 5495181 (1996-02-01), Kolze
patent: 5498975 (1996-03-01), Cliff et al.
patent: 5498979 (1996-03-01), Parlour et al.
patent: 5576554 (1996-11-01), Hsu
patent: 5677888 (1997-10-01), Lui et al.
patent: 5777887 (1998-07-01), Marple et al.
patent: 5815404 (1998-09-01), Goetting et al.
patent: 1-158764 (1989-06-01), None
Wey (“On yield consideration for the design of redundant programmable logic arrays”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, No. 4, Apr. 1988, pp. 528-535).*
Hasan et al. (“Minimum fault coverage in reconfigurable arrays”, Eighteenth International Symposium on Fault-Tolerant Computing, 1988, FTCS-18, Digest of Papers, Jun. 27, 1988, pp. 348-353).*
Hatori et al. (“Introducing redundancy in field programmable gate arrays”, Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, May 9, 1993, pp. 7.1.1-7.1.4).
Lacey Timothy
MacArthur James
Kik Phallaka
QuickLogic Corporation
Smith Matthew
Wagner , Murabito & Hao LLP
LandOfFree
Techniques and circuits for high yield improvements in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques and circuits for high yield improvements in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques and circuits for high yield improvements in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2489343