Technique using FIFO memory for booting a programmable...

Details Technique using FIFO memory for booting a programmable... Technique using FIFO memory for booting a programmable...

1992-07-28

2002-08-20

Banankhah, Majid (Department: 2151)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S002000, C713S100000, C710S104000

Reexamination Certificate

active

06438683

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to computer systems and, more particularly, to computer systems making use of one or more supplemental programmable microprocessors, also referred to as slave processors.
BACKGROUND OF THE INVENTION
More often than not, the design of a stand-alone computer represents a substantial number of compromises, resulting in a machine which performs a very large number of different tasks well but which may not excel at a few highly specialized tasks. To enable such a computer to perform the specialized tasks more effectively or more rapidly, its own programmable central processing unit (CPU) is commonly supplemented by one or more additional processors (sometimes referred to as slave processors), each of which is itself a programmable microprocessor. Supplementing a host computer's CPU with a slave processor for the purpose of processing digital images is a good example.
When operational, a slave processor is typically controlled by instructions contained in its own random access memory (RAM), a hardware element which retains information only as long as power remains applied to it. Before such a slave processor can become operational, a process needs to occur which resets the slave processor and causes it to begin running a set of instructions (program) from RAM. Most processors begin executing start-up code from a specific pre-designated location during an initial process called booting or bootstrapping. For this reason, the start-up code is often referred to as a boot or bootstrapping program. The boot process typically begins after power is applied to the processor and its RAM (a cold boot) or after the processor has been reset to its initial state with power already on (a warm boot). Once it begins, the boot process uses the boot program to tell the processor how to read operating instructions from designated sources into its RAM. For the host computer's own central processing unit (CPU), a read only memory (ROM) chip is usually first looked to as the source of the boot program which is to be executed. In the past, a slave processor typically has either been provided with its own ROM for this purpose or has been provided with a dual ported RAM which permits the host computer to download the boot program to be executed by the slave processor directly into the slave processor's own RAM.
Some microprocessors have an on-chip ROM that contains a generic loader program which facilitates the booting process. This small loader program starts running from the on-chip ROM when the microprocessor is reset and contains program instructions which move the program to be executed on the microprocessor from externally connected ROM to externally connected RAM. The data width of the externally connected ROM may not be the same as the externally connected RAM, thus permitting a reduction in the number of ROM devices required in a system.
Both of these commonly employed arrangements for booting up a slave processor have significant disadvantages. Providing the slave processor with its own ROM for booting purposes creates major disadvantages if the boot program stored in the ROM ever has to be changed. The ROM itself then has to be replaced, which is not only inconvenient but also can be quite expensive if a large number of systems are involved. In addition, a slave processor sometimes needs to communicate with the host CPU on a two way basis, and a ROM provides no such capability. Additional communication circuitry is then required. As to the alternative approach, a dual ported RAM not only is relatively expensive to use for booting purposes but also, because of its relative bulk, frequently requires more space than may be readily available in desk-top equipment. Furthermore, most dual ported RAM implementations do not allow simultaneous access to the RAM by both attached devices, which can adversely affect the speed of communications between the host computer and the slave processor.
SUMMARY OF THE INVENTION
The present invention solves these problems of the prior art simply and inexpensively by using a first in first out (FIFO) memory connected between the host computer and the slave processor. Broadly, the invention takes the form of a computer system comprising a host computer, a programmable microprocessor (the slave processor) controlled by the host computer, a FIFO memory connected between the host computer and the microprocessor, and means for providing a boot program and/or boot data from the host computer to the microprocessor through the FIFO memory. The boot program used by the microprocessor is easy to change since it is not located in ROM, the components in the system are reduced by the number of ROM's that would otherwise be required, and the FIFO memory is usable as a means for communicating with the host computer after the booting up stage has completed.
More specifically, the invention takes the form of a computer system comprising a host computer having an input/output (I/O) memory bus, a programmable microprocessor controlled by the host computer and having at least one memory bus of its own, a FIFO memory connected between the I/O memory bus of the host computer and a memory bus of the microprocessor, and means for providing a boot program and/or boot data from the host computer to the microprocessor through the FIFO memory.
In specific embodiments of the invention, the FIFO memory may comprise a single data item register, a unidirectional FIFO memory directed from the host computer to the slave processor, a bidirectional FIFO memory, or a pair of oppositely directed unidirectional FIFO memories.
The invention may be more fully understood from the following detailed description, taken in the light of the accompanying drawing and the appended claims.


REFERENCES:
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4975904 (1990-12-01), Mann et al.
patent: 4975905 (1990-12-01), Mann et al.
patent: 5136713 (1992-08-01), Bealkowski et al.
patent: 5155833 (1992-10-01), Cullison et al.
patent: 5210875 (1993-05-01), Bealkowski et al.
patent: 0268285 (1986-11-01), None
patent: 0262468 (1988-04-01), None
Research Disclosure, vol. 326, No. 093, Jun. 10, 1991, Ensworth, GB, pp. 457-459, “Apparatus for Programming a Peripheral Processor”.
IBM Technical Disclosure Bulletin, vol. 32, No. 9B, 2/90, New York, US, pp. 312-319, “Personal Computer System to Intel 80452-based Adapter Download Algorithm”.

Affiliated with

Also associated with

Rating

Technique using FIFO memory for booting a programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Technique using FIFO memory for booting a programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique using FIFO memory for booting a programmable... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2885199