Technique to simultaneously distribute clock signals and...

Details Technique to simultaneously distribute clock signals and... Technique to simultaneously distribute clock signals and...

2007-03-13

2007-03-13

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Systems using alternating or pulsating current

Angle modulation

C375S308000, C375S330000, C375S354000, C327S141000, C713S400000, C713S503000, C714S700000, C714S731000

Reexamination Certificate

active

11243825

ABSTRACT:
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

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patent: 6535071 (2003-03-01), Forbes
K. Yip, “Clock tree distribution: balance is essential for a deep-submicron ASIC design to flourish,” IEEE Potentials, vol. 16, No. 2, pp. 11-14, Apr.-May 1997.
K. M. Carrig et al., “A Clock methodology for high-performance microprocessors,” Proc. Custom Integrated Circuits Conference, Santa Clara, CA, May 5-8, pp. 119-122, 1997.
J. L. Neves et al., “Automated synthesis of skew-based clock distribution networks,” VLSI Design, vol. 7, No. 1, pp. 31-57, 1998.

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