Technique to prevent deprogramming a floating gate transistor us

Details Technique to prevent deprogramming a floating gate transistor us Technique to prevent deprogramming a floating gate transistor us

1994-07-05

1995-10-10

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

G11C 1134

Patent

active

054576539

ABSTRACT:
A novel method of connecting and operating an NVM transistor in the switching circuit is provided. A full voltage signal can be switched across an NVM transistor. The device is turned on prior to the signal switching and the electrical characteristics of the NVM device relative to the associated circuitry is carefully regulated to prevent the source-drain voltage from rising above a preselected maximum voltage (e.g. 1 v). Two embodiments of the present invention are described. In the first embodiment, the relative impedances of the NVM transistor and its driving circuit are controlled. The driver circuit and the NVM transistor switch act as a resistor divider circuit with a percentage of the full switching voltage appearing across the NVM transistor and the driver circuit according to their relative impedances. The second embodiment is applicable when the NVM transistor switch drives a capacitive load. The rise time of the signal to be switched is controlled. This can be done by controlling the driver circuit turn-on time, the relative resistor-capacitor (RC) risetime on either side of the NVM switch, or a combination of the two techniques. If the risetime of the switching signal is slow enough, the voltage at the output terminal of the NVM transistor closely follows the input voltage to minimize the source-drain voltage.

REFERENCES:
patent: 4870302 (1989-09-01), Freeman
patent: 5015885 (1991-05-01), Elgamal

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