Technique to obtain increased channel mobilities in NMOS...

Details Technique to obtain increased channel mobilities in NMOS... Technique to obtain increased channel mobilities in NMOS...

1999-06-28

2001-08-28

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S418000, C438S197000, C438S517000, C438S530000

Reexamination Certificate

active

06281532

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
A method of modifying the carrier mobility of a transistor is described. More specifically, the present invention describes a method of utilizing implants in a transistor gate to induce a mechanical stress and modify the carrier mobility of the transistor.
2. Description of Related Art
FIG. 1
is a side cross-sectional view of an NMOS transistor
10
known in the art. A conventional transistor
10
generally includes a semiconductor generally comprising a silicon layer
16
having a source
20
and a drain
18
separated by a channel region
22
. A thin oxide layer
14
separates a gate
12
, generally comprising polysilicon, from the channel region
22
. In the device
10
illustrated in
FIG. 1
, the source
20
and drain
18
are n+ regions having been doped by arsenic or phosphorous. The channel region
22
is generally boron doped. (Note that for both the source
20
and drain
18
regions and the channel region
22
other materials may also be used.) Fabrication of a transistor such as the device
10
illustrated in
FIG. 1
is well-known in the art and will not be discussed in detail herein.
The speed or velocity (v) of the current through the channel region
22
is a function of the mobility (&mgr;) of the channel region, as expressed by the formula v=&mgr;&Egr; wherein &Egr; represents the electric field across the channel region
22
. Because &Egr; is generally a constant value, the higher the carrier mobility (&mgr;) of a device the faster the device can function. As the demand for faster devices continually grows in the industry, the desire for a device having an increased mobility also increases. Thus, a method for fabricating a device having an increased carrier mobility would be desirable.
Another issue that arises when dealing with transistors of the present art involves current leakage from the source to the drain. One of the limiting factors in the scaling of transistors to smaller dimensions is the inability of the gate to fully control the channel region below the gate. As the source and drain junctions approach one another, the lines of force resulting from the potential applied to the drain terminate on the source junction, causing Drain-induced Barrier Lowering (DIBL). This DIBL results in leakage current between the source and drain, and at short enough channel lengths, results in failure of the device. Thus, a method of reducing current leakage would allow for the fabrication of transistors fabricated on a smaller scale.
SUMMARY OF THE INVENTION
A method of modifying the carrier mobility of a transistor is described. First, a transistor having a gate is formed. A substance is then implanted in the gate. The transistor is annealed such that the implanted substance forms at least one void in the transistor's gate.


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